Backside Power Delivery Network

Backside power delivery network (BSPDN) is the generic name for moving a chip's power wiring to the back side of the wafer, separate from the signal wiring on the front, and it describes a physical answer to a routing and voltage-drop problem every foundry pursuing sub-2nm-class logic has had to solve — not any single company's branded product. The three leading foundries each ship or plan their own named implementation of this idea: Intel calls its version PowerVia, TSMC calls its planned version Super Power Rail, and Samsung has its own backside power delivery network without a single widely used standalone brand name. How a foundry gets from conventional frontside power to a working backside power grid looks roughly like this:

Frontside power hits a wall
IR drop and routing congestion both worsen as wiring shrinks
Backside power adopted
Power grid moved to the wafer's rear side
Each foundry's own buildSame architecture, different process and name
Wafer thinned from the back
Exposes backside after frontside build completes
Through-wafer vias formed
Connect backside rail to transistor source/drain
Backside metal grid built
Thick copper power routing, decoupled from signal wiring
Foundry names its device
PowerVia, Super Power Rail, or unbranded BSPDN
↻ next node generation
Qualified for production
Each foundry on its own node and schedule

A few things are worth knowing about why backside power delivery is an architecture, not a single company's product:

The problem BSPDN solves is that signal wiring and power wiring have been fighting for the same frontside metal layers, and that fight gets worse every node. In conventional chip construction, both the power grid and the signal routing share the same stack of copper layers built on the wafer's front, which means as that stack is asked to carry more signal traffic at tighter pitch, the power grid either gets squeezed into thinner, higher-resistance wires or has to compete for routing space — Intel reached a version of this wall that led to PowerVia debuting alongside RibbonFET on Intel 20A, while TSMC chose to ship its gate-all-around nanosheet transistor on N2 with conventional frontside power first, planning Super Power Rail for A16 instead.

Frontside vs. Backside Power Delivery one architecture, adopted by every foundry under its own name and schedule CONVENTIONAL FRONTSIDE POWER signal + power share frontside metal transistor layer IR drop can reach ~20% of supply budget BACKSIDE POWER DELIVERY frontside: signal wiring only transistor layer, backside vias backside: thick copper power grid IR drop collapses, congestion drops each company qualifies its own backside power network under its own name — Intel's PowerVia (20A, 18A), TSMC's Super Power Rail (targeted A16), and Samsung's own backside power delivery network "BSPDN" and "backside power delivery" describe the architecture every one of these shares — not a single product

Through-wafer vias are the specific mechanism that every company's backside power implementation has to get right, and getting it wrong either damages the transistor above or fails to make reliable contact. Connecting a backside power rail to a transistor's source and drain requires via structures that punch through the thinned wafer at a scale fine enough not to disturb delicate gate-all-around structures sitting just above — Intel's PowerVia uses nano-through-silicon-vias sized for its RibbonFET geometry, and TSMC's planned Super Power Rail will need an equivalent via structure sized for its own nanosheet transistor, which is why neither company's via design transfers directly to the other's device.

"BSPDN" and "backside power delivery" are the right terms when no company is named; "PowerVia" and "Super Power Rail" are the right terms when one is. This article covers the architecture and the interconnect physics that PowerVia, Super Power Rail, and Samsung's own backside power network all share. For what distinguishes each company's specific implementation — its qualification node, its paired transistor architecture, and its own generation-to-generation roadmap — see PowerVia and Super Power Rail directly, since each of those is a specific company's own platform built on the generic architecture described here.

Read backside power delivery the way this whole node-naming lineage keeps asking to be read: as a physical answer to a physical problem, arrived at independently by every foundry that needed one, where the generic term names the architecture and the company's own brand name — PowerVia, Super Power Rail, or Samsung's unbranded implementation — names that company's own platform, not a ruler the rest of the industry shares.

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