Backside Power Bspdn

Backside Power Delivery Network (BSPDN) — commercially known as Intel PowerVia, TSMC Super Power Rail (SPR), and Samsung BSPDN — is the most profound interconnect architecture transformation in fifty years of silicon manufacturing. For the entire history of integrated circuits, transistors sat at the bottom of the wafer while all power lines and signal lines shared the same crowded Back-End-of-Line (BEOL) metal stack on the front. At 2 nm and below, signal wires have become so dense and fine-pitched that routing power through the front causes catastrophic resistance, severe voltage drops, and severe routing congestion. BSPDN physically splits the interconnect network: the front of the die carries 100% of the high-speed signal wires, while a dedicated, low-resistance thick-copper power grid is built on the backside of the silicon substrate, feeding current directly into the source and drain terminals of transistors through nano-Through-Silicon Vias (nano-TSVs).

The routing bottleneck and the physics of IR drop. In a conventional frontside power delivery network, power ($V_{DD}$) and ground ($V_{SS}$) must fight with signal wires across 15 to 20 metallization layers (M0 up to M18+). The upper metal layers are thick and carry power across the chip, but as current steps down through dozens of successively thinner vias to reach the standard cells at M0, resistance escalates exponentially. The cross-sectional area of M0 wires shrinks to less than $20 \times 20\text{ nm}$, where electron scattering against grain boundaries and sidewalls drastically increases copper resistivity. The total voltage drop across the power grid follows Ohm's law integrated across every via and wire segment:

At sub-2nm nodes running at 0.7 V supply voltage, frontside IR drop can consume 15% to 20% of the entire voltage margin ($\Delta V > 100\text{ mV}$). Transistors starve for current under peak transient load, clock frequency droops, and designers are forced to dedicate up to 30% of critical lower-level metal tracks purely to fat power rails. This robs standard cells of routing space and limits standard cell scaling.

How BSPDN solves the problem. By routing power from the back of the wafer, the entire dynamic reverses:
1. Direct transistor connection. Power no longer cascades down 15–20 resistive frontside metal layers. Instead, power enters from wide, thick copper rails fabricated on the rear of the wafer and travels just a few hundred nanometers through nano-TSVs or Buried Power Rails (BPR) directly into the transistor source and drain.
2. IR drop reduction. Path resistance from the power grid to the transistor drops by roughly $4\times$ to $6\times$, slashing IR drop to under 3% of supply voltage. This lets the chip sustain higher frequencies or operate at a lower supply voltage with equal switching performance.
3. Standard cell scaling (Track Height compression). Eliminating frontside power rails frees up the congested M0 and M1 metal layers. Standard cell heights that were stuck at 6-track (6T) can shrink to 5-track (5T) or even 4-track (4T), enabling 15% to 20% cell area reduction purely from interconnect architecture without changing transistor pitch.
4. Zero signal-power crosstalk. Separating noisy power rails from high-speed digital clock and data lines sharply suppresses capacitive and inductive coupling noise.

The manufacturing sequence: precision wafer bonding and extreme thinning. Building BSPDN requires an intricate double-sided fab sequence. The frontside transistor layers and all signal BEOL metal layers are fabricated first. The processed wafer is then flipped and bonded face-down to a structural silicon carrier wafer using dielectric fusion bonding. The silicon substrate of the active wafer is then ground down, etched, and polished using Chemical Mechanical Planarization (CMP) from an initial 775 µm thickness down to less than 1 µm — leaving only a razor-thin active silicon layer. Lithography then patterns nano-TSVs from the backside with sub-5 nm overlay accuracy to align with transistor source/drain contacts, followed by deposition of thick backside copper power rails (B0, B1, B2).