Nano-TSV
Nano-TSVs are the sub-micron through-silicon vias that carry power from the back of a thinned wafer to the buried power rails sitting just beneath the transistors. They are what makes backside power delivery an electrical reality rather than a layout idea, and they are a different device from the package-level TSV that shares the name.
Two orders of magnitude apart
| Interposer TSV | Nano-TSV | |
|---|---|---|
| Diameter | 5–10 µm | 100–500 nm |
| Depth | 50–100 µm | 200–500 nm |
| Aspect ratio | 10–20:1 | ~10:1 |
| Pitch | 40–100 µm | sub-micron |
| Lands on | package RDL | buried power rail |
| Keep-out zone | 3–10 µm | small |
| Limiting physics | mechanical stress | resistance |
The aspect ratio is similar; everything else differs by two orders of magnitude. The consequence is that the two are limited by opposite mechanisms. An interposer TSV is constrained by the stress it projects into surrounding silicon, since the keep-out zone scales with via radius and sterilises area quadratically. Shrink the via to a few hundred nanometres and that penalty largely evaporates — but resistance, which scales as
becomes brutal. Halving the diameter quadruples resistance, and a nano-TSV is already two orders of magnitude narrower than its package-level cousin. The engineering fight in BSPDN is therefore conductance, not mechanics.
The buried power rail it lands on
A nano-TSV terminates on a buried power rail: a trench cut into the shallow-trench isolation below the device layer and filled with a refractory metal before the transistors are finished. Tungsten and ruthenium are the candidates, chosen because they survive the full subsequent thermal budget — copper does not, and would contaminate the device layer besides.
Burying the rail removes $V_{DD}$ and $V_{SS}$ from the cell's metal stack, which is what releases routing tracks and takes standard cells below 5T. But a buried rail is small, and a small refractory conductor has high resistance, so the rail can only be short: it must be re-fed from the backside network frequently. Nano-TSV pitch is therefore set by the acceptable IR drop along the rail between feed points, not by how densely vias could be patterned.
The contact is usually the limit
Total path resistance from backside metal to device is the sum of three terms:
Backside metal is thick and wide, so $R_{\text{bsm}}$ is negligible — that is the entire point of the architecture. The via body contributes meaningfully. But the interface where the nano-TSV meets the buried rail has an area set by a via a few hundred nanometres across landing on a rail a few tens of nanometres wide, and with $R_c$ inversely proportional to that area, it typically dominates. This is why low-temperature silicide and ALD barrier metallurgy on the backside receive attention out of proportion to their apparent simplicity.
Process integration
The sequence is demanding because it happens to a finished wafer. The device wafer is bonded face-down to a carrier, ground and then etched to a few hundred nanometres, stopping on a buried etch-stop layer — usually a SiGe marker placed during epitaxy, since a timed grind cannot hold that tolerance. Vias are then patterned from the back, aligned to front-side features read through the remaining silicon, etched, lined by ALD barrier, and filled.
Every step is capped near 400 °C because the full BEOL already exists on the other face. Overlay is referenced through the substrate rather than to a surface mark, and the accuracy achievable there sets how small the via can be — a misregistered nano-TSV either misses its rail or shorts to an adjacent node. Neither is repairable.
The trade-off in one line
More vias mean lower rail IR drop but more device area consumed and more of the thermal path replaced by metal and bonding interfaces. Fewer vias mean a cleaner device layer and a worse power grid. Backside power delivery is, in the end, an optimisation over nano-TSV pitch, and every other parameter in the architecture is downstream of that choice.