Bspdn Walk Through Wafer Flip and Carrier Bonding

# Backside Power Delivery: Step 5 — Walk Through Wafer Flip and Carrier Bonding

## 1. A Process Sequence Most Prior Nodes Never Needed

Everything described so far motivates BSPDN; this step begins the "how." Accessing the back
side of a wafer that was built entirely from the front requires a process sequence that most
prior transistor generations simply never needed, because they never had any reason to touch
the wafer's rear face after frontside fabrication finished.

## 2. Bonding to a Carrier Wafer

Before the device wafer can be flipped, its fragile, fully-processed frontside -- transistors,
contacts, and however many signal metal layers have already been built -- must be protected.
A separate carrier wafer is bonded face-to-face onto the device wafer's frontside, providing
mechanical support for everything that follows. The bond must survive grinding, chemical
exposure, and subsequent thermal steps without delaminating or introducing stress that would
distort the already-finished transistor layer beneath it.

## 3. The Flip

Once bonded, the combined wafer pair is flipped, so that what was the wafer's original back
side -- previously just bulk, unused silicon -- now faces upward and becomes accessible for
new processing. The transistor layer and its frontside interconnect are now sandwiched between
the carrier (above, in the flipped orientation) and the exposed original backside (now facing
the tools).

## 4. Setting Up Thinning

With the wafer flipped and mechanically supported by the carrier, the next step can begin
grinding and thinning away the bulk of the original substrate -- several hundred microns of
silicon that served no electrical purpose once the transistor layer was built, and that must
now be removed to expose a thin enough membrane for nano-TSVs to reach through it.

Carrier Bonding: Protecting the Finished Frontside a temporary carrier wafer supports the device wafer through the flip DEVICE WAFER: TRANSISTORS AND FRONTSIDE METAL ALREADY BUILT Transistor / Channel Layer Thinned Substrate / Via Field CARRIER WAFER BONDED FACE-TO-FACE BEFORE ANY FLIP Power Trunk Return Trunk Signal Power the bond must survive grinding and thermal steps without distortion this sequence is new relative to conventional frontside-only processing
Backside Power Delivery: Step 5 — Walk Through Wafer Flip and Carrier Bonding Interconnect decoupling, nano-TSV/buried power rails, and standard-cell scaling A PROCESS SEQUENCE MOST PR... Thinned Si Substrate <500nm Frontside Signal M0-M6 Backside Power B0-B3 Backside Power Delivery Everything described so far motivates BSPDN; this step begins the "how." Accessing the back side of a wafer that was built entirely from the front requires a process BONDING TO A CARRIER WAFER Thinned Si Substrate <500nm Carrier Wafer Device Layer (Flipped) Fusion Bonding & CMP Before the device wafer can be flipped, its fragile, fully-processed frontside -- transistors, contacts, and however many signal metal layers have already been THE FLIP Thinned Si Substrate <500nm Carrier Wafer Device Layer (Flipped) Fusion Bonding & CMP Once bonded, the combined wafer pair is flipped, so that what was the wafer's original back side -- previously just bulk, unused silicon -- now faces upward Key Semiconductor Engineering Takeaway BSPDN Step 5 uncouples power delivery from signal routing to resolve advanced node interconnect bottlenecks. Essential companion architecture deployed across 2nm and sub-2nm nodes by Intel, TSMC, and Samsung.

Take bspdn walk through wafer flip and carrier bonding further

Ask the copilot about this term, or have our engineers assess it against your process.

Ask CFSGPT about this → Request a technical assessment → Open the CFS app