Bspdn Walk Through Wafer Thinning and Backside Reveal

# Backside Power Delivery: Step 6 — Walk Through Wafer Thinning and Backside Reveal

## 1. From Hundreds of Microns to a Few Hundred Nanometers

A finished device wafer, before thinning, is typically several hundred microns thick --
mechanically sturdy but electrically irrelevant beyond the top few microns where the
transistor layer sits. Backside processing needs to remove essentially all of that bulk
silicon, leaving only a thin membrane a few hundred nanometers thick directly beneath the
transistor layer.

## 2. Coarse Grinding, Then Precision Removal

Thinning happens in stages. Coarse mechanical grinding removes the bulk of the unwanted
silicon quickly but leaves a rough, damaged surface and imprecise thickness control. A
subsequent chemical-mechanical polishing and selective etch step removes the remaining
material more slowly and precisely, stopping at or near a buried etch-stop layer that was
deliberately built into the wafer during frontside processing specifically to give this later
step a reliable stopping point.

## 3. Why Precision Matters So Much Here

Unlike ordinary wafer-thinning steps used in some packaging flows, this thinning must stop
within a tight thickness tolerance across the entire wafer, because the nano-TSVs formed in
the next step need to land precisely on buried power rails that sit at a known, shallow depth.
Too little removal leaves excess silicon between the via and its target; too much removal risks
damaging the transistor layer itself.

## 4. The Reveal

Once thinning reaches its target thickness, the wafer's original back side is considered
"revealed" -- exposed, thinned, and ready for the backside lithography and via-etch steps that
follow. This reveal is the point at which the wafer first becomes accessible for genuinely new
backside interconnect formation, rather than merely flipped bulk silicon.

Grinding and Thinning to a Buried Etch-Stop Layer coarse grinding followed by precision polish and selective etch BULK SILICON: SEVERAL HUNDRED MICRONS, REMOVED IN STAGES Transistor / Channel Layer Thinned Substrate / Via Field THINNED MEMBRANE: A FEW HUNDRED NANOMETERS, TARGET THICKNESS Power Trunk Return Trunk Signal Power the etch-stop layer gives this step a reliable, repeatable stopping point thickness uniformity across the wafer is the main process-control challenge
Backside Power Delivery: Step 6 — Walk Through Wafer Thinning and Backside Reveal Interconnect decoupling, nano-TSV/buried power rails, and standard-cell scaling FROM HUNDREDS OF MICRONS T... Thinned Si Substrate <500nm Frontside Signal M0-M6 Backside Power B0-B3 Backside Power Delivery A finished device wafer, before thinning, is typically several hundred microns thick -- mechanically sturdy but electrically irrelevant COARSE GRINDING, THEN PREC... Thinned Si Substrate <500nm Carrier Wafer Device Layer (Flipped) Fusion Bonding & CMP Thinning happens in stages. Coarse mechanical grinding removes the bulk of the unwanted silicon quickly but leaves a rough, damaged surface and imprecise WHY PRECISION MATTERS SO M... Thinned Si Substrate <500nm Frontside Signal M0-M6 Backside Power B0-B3 Backside Power Delivery Unlike ordinary wafer- thinning steps used in some packaging flows, this thinning must stop within a tight thickness tolerance across the entire wafer, Key Semiconductor Engineering Takeaway BSPDN Step 6 uncouples power delivery from signal routing to resolve advanced node interconnect bottlenecks. Essential companion architecture deployed across 2nm and sub-2nm nodes by Intel, TSMC, and Samsung.

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