Bspdn Examine TSMC Super Power Rail Distinct Implementation

# Backside Power Delivery: Step 16 — Examine TSMC Super Power Rail as a Distinct Implementation

## 1. A Separate Named Approach, Not a Copy of PowerVia

TSMC has publicly described its own backside power delivery implementation under the name
Super Power Rail, positioned for introduction at a more advanced node than PowerVia's initial
deployment. While both follow the shared BSPDN architecture this series has described, TSMC's
public disclosures describe implementation choices distinct from Intel's.

## 2. Emphasis on the Buried Rail Interface

TSMC's public positioning for Super Power Rail places particular emphasis on the buried power
rail and its direct interface to the transistor's source and drain contacts -- the structure
this series described in Steps 8-9 -- as a central element of its approach, with the "Super
Power Rail" name itself referring to that buried-rail structure specifically rather than to the
backside metal network as a whole.

## 3. Stated Timing and Node Pairing

TSMC has publicly associated Super Power Rail with a more advanced node generation than
PowerVia's initial introduction, consistent with this series' Step 14 observation that BSPDN
implementations tend to debut alongside the densest available transistor architectures, where
the economics of absorbing backside processing's added cost and yield risk (Steps 12-13) are
most favorable.

## 4. What Remains Consistent Across Implementations

Despite differences in naming, timing, and specific emphasis, TSMC's publicly described
approach shares the same core mechanism this series has traced throughout: wafer flip and
thinning, nano-TSV formation, and a buried-rail interface to the transistor contacts. Step 18's
side-by-side comparison examines these differences and similarities directly, once Samsung's
approach has also been introduced in Step 17.