Bicmos Logic 1980s Measure Propagation Delay Against Pure CMOS at Matched Load

# BiCMOS Logic (Late 1980s): Step 8 — Measure Propagation Delay Against Pure CMOS at Matched Load

## 1. Setting Up a Fair Comparison

To make Steps 6 and 7's circuit-level claim measurable, this step compares propagation delay for a BiCMOS output buffer against a pure CMOS output buffer, both driving the same external load capacitance $C_L$, both fabricated on comparable process geometry. The CMOS buffer's delay is dominated by its output transistors charging $C_L$ through their own channel resistance, following the same $t_{pd} \approx 0.69 \, R_{on} C_L$ relationship that governs any single-stage CMOS driver; the BiCMOS buffer's delay instead reflects the bipolar output transistor's much lower effective output impedance while saturated, plus a small added delay from the CMOS-to-bipolar base-drive stage itself.

## 2. Where the Numbers Land

At loads in the range representative of a long on-chip bus line or an output pad — tens to a few hundred picofarads — contemporaneous measurements on production BiCMOS processes typically showed the BiCMOS buffer completing the same transition in roughly half to a third of the time the equivalent pure CMOS buffer needed, with the advantage growing as $C_L$ grows, because the bipolar stage's low output impedance keeps $R_{on}C_L$ small even as $C_L$ increases, while the CMOS buffer's resistance-dominated charging time scales directly with $C_L$ with no such compensating advantage.

## 3. Companion Diagram One: Quantitative View

Propagation Delay vs Load: BiCMOS Pulls Away as C_L Grows t_pd against load capacitance, matched process geometry pure CMOS buffer — delay scales directly with C_L BiCMOS buffer — low output impedance holds delay down gap widens, it does not close, as load grows t_pd ≈ 0.69 · R_on · C_L, R_on fixed and sizeable bipolar saturation keeps effective R_on far lower at large C_L, BiCMOS commonly halves or thirds the delay pure CMOS needs the advantage is a direct consequence of the bipolar stage's low output impedance

## 4. Companion Diagram Two: Structural View

Same Load, Same Geometry, Different Output Impedance what each buffer's output stage presents to the identical load CMOS OUTPUT STAGE R_on set by channel width — a real, sizeable resistance IDENTICAL LOAD C_L same external capacitance for both measurements BIPOLAR OUTPUT STAGE saturated BJT — much lower effective output impedance the fair comparison isolates the output stage as the only real variable

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