Bipolar Ecl 1960s Match Transmission Line Interconnect at Ecl Speeds
# Bipolar ECL Logic (1960s): Step 12 — Matching Transmission-Line Interconnect at ECL Speeds
Why ECL boards could not be wired like RTL or DTL boards. At the 1-4 nanosecond edge rates typical of 1960s ECL gates, a signal's wavelength on a typical PCB trace becomes comparable to the trace lengths used on a real backplane, and an unterminated or poorly matched trace behaves as a transmission line that reflects a meaningful fraction of the signal back toward the source — a phenomenon that simply does not matter at the much slower edge rates of RTL or DTL. This step covers why ECL specifically forced transmission-line discipline on digital board designers years before it became a general concern.
## 1. When a Trace Stops Being 'Just a Wire'
A PCB trace behaves electrically as a simple low-impedance connection as long as the signal's rise time is long compared to the trace's signal propagation delay (roughly 150-180 picoseconds per inch for typical FR-4 stripline or microstrip geometry). ECL's 1-2 nanosecond edge rates meant that any trace longer than a few inches had a propagation delay that was no longer negligible compared to the edge rate, and an impedance mismatch at either end of such a trace — at the driving emitter follower, or at the receiving current-switch base — reflects part of the incident wave back down the line, arriving back at the source as a secondary, delayed step that can corrupt the logic level seen at the far end during the critical decision window.
## 2. Real Diagram: Terminated vs. Unterminated ECL Trace Waveforms
## 3. The Standard Fix: Controlled Impedance Plus Termination
ECL system designers adopted controlled-impedance traces (commonly 50 ohms, matching readily available coaxial and stripline practice) and terminated the receiving end with a resistor to the negative supply rail sized to match that impedance, which absorbs the incident wave at the receiver rather than letting it reflect. This discipline — characteristic impedance control, matched termination, and attention to via and connector discontinuities — was a foreign concept to most digital logic designers of the era, who were used to thinking of interconnect as ideal wires, and it is one of the most lasting non-circuit legacies of 1960s ECL: the transmission-line-aware board design practice it forced became standard practice for all high-speed digital interconnect once clock rates in TTL and later CMOS logic caught up to ECL's edge rates decades later.
## 4. Companion Diagram: Stage Sequence and Trend Summary
## Matching Transmission-Line Interconnect at ECL Speeds's Place in the Process Lineage
This is step 12 of 20 in the Bipolar ECL Logic (1960s) series, covering the transmission-line matching discipline that ECL's fast edge rates required years before other logic families needed it.