bowing

Bowing is an etch profile defect in semiconductor plasma etching where the sidewalls of a trench or hole feature develop a convex curvature, becoming wider in the middle than at the top or bottom. This creates a barrel-shaped or bowed cross-sectional profile instead of the desired vertical sidewalls. Bowing results from the interaction between directional ion bombardment and isotropic chemical etching at different depths within the feature. The primary mechanism involves ions that strike the feature sidewalls after being deflected from their vertical trajectory. Near the feature opening, ions arriving at oblique angles impact the upper sidewalls and scatter downward, but the maximum flux of deflected ions occurs at a depth corresponding to roughly one-third to one-half of the feature depth, where accumulated sidewall sputtering and enhanced chemical etching create the maximum lateral recess. Additionally, energetic ions that reflect from the feature bottom can strike the lower sidewalls, but their energy is reduced after the first collision, resulting in less etching. This differential sidewall erosion produces the characteristic bowed shape. Bowing is exacerbated by: high bias power (more energetic ions with wider angular distribution), low chamber pressure (longer mean free path, more directional but higher-energy ions that scatter more effectively from surfaces), inadequate sidewall passivation, and high aspect ratios where ion angular distributions within the feature become complex. Bowing is particularly problematic in high-aspect-ratio silicon trench etching for DRAM capacitors and 3D NAND structures, where it can cause electrical shorts between adjacent features or inadequate dielectric isolation. Mitigation strategies include optimizing the passivation chemistry to deposit protective films on sidewalls (using gases like C4F8, SiCl4, or O2 additions), reducing ion energy during the main etch step, implementing multi-step etch recipes with alternating etch and passivation phases, and carefully controlling wafer temperature to manage passivation film stability.