burn-in test
**Burn-In Test** is an **accelerated reliability screening technique that operates ICs at elevated temperature and voltage to precipitate early failures before product shipment** — eliminating infant mortality devices from the shipped population.
**Bathtub Curve and Infant Mortality**
- Semiconductor failure rate follows a bathtub curve:
1. **Infant Mortality**: High early failure rate (latent defects).
2. **Useful Life**: Low, stable failure rate.
3. **Wear-Out**: Increasing failure rate at end of life.
- Burn-in stresses devices to "age" them past the infant mortality region before shipping.
**Types of Burn-In**
- **Static Burn-In**: Device powered with static voltage, no switching. Low cost, limited stress.
- **Dynamic Burn-In (BIBI)**: Device exercised with functional patterns during burn-in. More effective at catching dynamic failures.
- **System-Level Burn-In**: PCB/system level — most expensive, finds system interaction failures.
**Acceleration Factors**
- **Arrhenius Model**: $AF = e^{\frac{E_a}{k}(\frac{1}{T_{use}} - \frac{1}{T_{burn-in}})}$
- $E_a$ = activation energy (~0.7 eV for most mechanisms).
- Typical burn-in: 125–150°C for 48–168 hours → equivalent to years of use.
- Voltage acceleration: Oxide defects accelerate with $V^n$ (n~2–3).
**HTOL (High Temperature Operating Life)**
- JEDEC standard (JESD22-A108): 1000 hours at 125°C, Vmax.
- Qualifies device reliability for specific use environments.
- Provides MTF (Mean Time to Failure) data for reliability projections.
**Burn-In Board and Socket**
- High-temperature burn-in sockets: Must withstand repeated insertion, 200°C rating.
- Burn-in boards: Custom for each package type.
- BIBI: Burn-in board electronics generate test patterns at temperature.
**Industry Trend**
- Burn-in cost is high ($0.50–$5.00 per device). Auto/industrial: Still widely used.
- Consumer: Reduced/eliminated as process defect density improved.
- AI chips (GPU, TPU): Burn-in at system level before datacenter deployment.
Burn-in testing is **the reliability insurance of the semiconductor industry** — a well-designed burn-in specification catches the fraction of latent defects that wafer test misses, protecting end-system reliability.