cache coherence

**Cache Coherence** — the mechanism that ensures all CPU cores see a consistent view of shared memory, even though each core has its own private cache. **The Problem** - Core A caches variable X = 5 - Core B writes X = 10 to its cache - Without coherence, Core A still sees X = 5 — stale data **MESI Protocol** (most common) - **Modified (M)**: Cache has the only valid copy, it's been written. Must write back to memory before others can read - **Exclusive (E)**: Cache has the only copy, matches memory. Can be written without bus transaction - **Shared (S)**: Multiple caches have this copy, matches memory. Read-only - **Invalid (I)**: Cache line is not valid **How It Works** 1. Core A reads X → gets Exclusive (only copy) 2. Core B reads X → Both get Shared 3. Core A writes X → A gets Modified, B's copy becomes Invalid 4. Core B reads X → A writes back, both get Shared again **Performance Implications** - **False Sharing**: Two variables in the same cache line (64 bytes) cause constant invalidation even if different cores access different variables. Fix: Pad data to cache line boundaries - Coherence traffic can become a bottleneck with many cores (>64) **Cache coherence** is transparent to software but its effects on performance (false sharing, cache ping-pong) must be understood for efficient parallel programming.