cache coherence protocol

**Cache Coherence Protocols** are the **hardware mechanisms that maintain a consistent view of shared memory across multiple processor cores' private caches — ensuring that when one core modifies a cached copy of a memory location, all other cores' copies are invalidated or updated, providing the illusion of a single unified memory despite the physically distributed cache hierarchy that is essential for multicore processor performance**. **The Coherence Problem** Each core has its own L1/L2 cache for fast access. When Core 0 writes to address X (cached locally), Core 1's copy of X in its cache becomes stale. Without coherence, Core 1 reads the old value — a silent data corruption bug. The coherence protocol ensures that every read returns the most recently written value, regardless of which core performed the write. **MESI Protocol** The most widely-used snooping protocol. Each cache line is in one of four states: - **Modified (M)**: This cache has the only valid copy, and it is dirty (different from main memory). This cache must write back before another cache can read. - **Exclusive (E)**: This cache has the only copy, and it is clean (matches memory). Can transition to M without bus traffic (silent upgrade). - **Shared (S)**: Multiple caches may hold copies, all clean. Must invalidate others before writing. - **Invalid (I)**: Not present in this cache. Must fetch from memory or another cache. **MOESI Extension**: Adds **Owned (O)** state — this cache has a dirty copy but others may have Shared copies. The owner supplies data on snooped reads without writing back to memory first. Used by AMD processors to reduce memory traffic. **Coherence Mechanisms** - **Snooping**: Every cache monitors (snoops) a shared bus for transactions. When Core 0 reads X, all other caches check if they hold X and respond accordingly. Scales to ~8-16 cores. Used in Intel's ring bus architectures. - **Directory-Based**: A centralized or distributed directory tracks which caches hold which lines. On a write, the directory sends targeted invalidations only to caches holding copies — no broadcast needed. Scales to hundreds of cores. Used in Intel Xeon Scalable (mesh interconnect), AMD EPYC, and ARM Neoverse. **False Sharing** Two variables on the same cache line (typically 64 bytes) accessed by different cores. Even though they are logically independent, the coherence protocol bounces the cache line back and forth between cores on every write — the line is shared but each core's write invalidates the other's copy. Performance impact: 10-100x slowdown on tight loops. Fix: pad variables to cache-line boundaries (`alignas(64)`). **Performance Impact** - **Cache-to-Cache Transfer Latency**: When Core 0 reads a line Modified in Core 1's cache, the transfer takes 40-100 ns (vs. ~4 ns L1 hit). Coherence traffic directly reduces effective memory bandwidth. - **Scalability Limit**: Snoop bandwidth limits snooping protocols. Directory storage overhead (bits per line × total cores) limits directory protocols. Both create a practical scalability ceiling. **Cache Coherence Protocols are the invisible contract that makes shared-memory multicore processors work** — the hardware mechanism that hides the complexity of distributed caches behind the programmer-friendly abstraction of a single, consistent memory space.