Capacitive DAC

A capacitive DAC, often called a CDAC or charge-redistribution DAC, converts a digital code into an analog voltage using nothing but a binary-weighted array of capacitors and conservation of charge — no resistors, no current sources, and no external reference ladder, which is exactly why it became the standard digital-to-analog core at the heart of most successive-approximation ADCs.

The array's topology is deceptively simple: capacitors sized C, 2C, 4C, 8C, and so on through however many bits the converter resolves, all with their top plates tied together at one common node, and each bottom plate switched independently between a reference voltage and ground. The common node's voltage settles purely by charge conservation — the total charge on the array before and after any switch transition has to balance, and because each capacitor's contribution to that balance is weighted by its own capacitance, the resulting common-node voltage is a weighted average set directly by which bottom plates happen to be connected to the reference at any given moment. Flip one bit's switch from ground to the reference, and the common node shifts by an amount proportional to that bit's own capacitor weight relative to the total array capacitance — exactly the binary-search step a successive-approximation conversion needs at each decision.

The same physical capacitor array that performs this digital-to-analog conversion also serves as the converter's own sample-and-hold element, a dual role that is the specific reason CDACs dominate SAR ADC design rather than a separate sample-and-hold feeding a conventional DAC. During the acquisition phase, the entire array samples the analog input directly, with every bottom plate connected to the input signal through the same sampling switch this series has already covered in detail — a bootstrapped switch, specifically, because the array's own settling accuracy during acquisition depends on exactly the signal-independent on-resistance bootstrapping provides. Once acquisition ends, the array switches into conversion mode, and that identical charge — now held on the array rather than still connected to the input — gets redistributed bit by bit as the SAR algorithm steps through its binary search, with no separate DAC circuit needed at all.

A CDAC's settling speed during each bit decision is governed by an RC time constant set by the switch resistance connecting each capacitor to its reference, which is exactly where the same on-resistance linearity problem bootstrapping solves reappears inside the converter's own core, not just at its input. Every bit decision in a SAR conversion requires the array to settle to a new voltage before the comparator can make a reliable decision, and a signal-dependent switch resistance anywhere in that reference-switching path introduces the identical settling-time distortion mechanism already covered for the input sampling switch — which is why high-resolution SAR ADC designs often need careful switch design throughout the reference network, not only at the single input sampling switch most discussions focus on.

The array's linearity instead depends entirely on how precisely the binary capacitor ratios actually hold in real silicon, which is a device-matching problem this series has already built the standard circuit-level answer for. A CDAC's fundamental assumption — that the 2C capacitor really does equal exactly twice the C capacitor, that 4C really is exactly twice 2C, and so on through the whole array — is never perfectly true in fabricated silicon, and any deviation from those exact binary ratios shows up directly as differential and integral nonlinearity in the converter's transfer function, since the DAC's output codes no longer land at their intended evenly-spaced voltage levels. Common-centroid layout, already covered in this series as the standard technique for matching device pairs against process gradients, is exactly what CDAC layout relies on at array scale — unit capacitor elements arranged symmetrically so that each binary-weighted capacitor is built from the same number of identical unit elements, distributed spatially to average out the same gradient-driven mismatch common-centroid layout was originally covered to solve for a single differential pair.

The tradeoff against a resistor-ladder DAC is almost entirely in the CDAC's favor for this specific application, which is why it won out as the dominant SAR ADC architecture rather than remaining one option among several. A resistor ladder draws continuous static current through its resistor string regardless of what code it's currently outputting, a real and unavoidable power cost; a capacitor array, once settled, draws essentially no current at all, since a charged capacitor holds its voltage without continuous current flow. This static-power advantage, combined with the dual sample-and-hold-plus-DAC role no resistor ladder can offer, is why nearly every modern SAR ADC built in a standard CMOS process uses a capacitive DAC rather than a resistive one, even though resistor ladders remain common in other converter architectures that don't share the SAR algorithm's specific need for repeated, settled comparisons against the same held charge.

A capacitive DAC is where two separate circuit-design disciplines this series has already covered converge inside a single physical structure — bootstrapped switches keep the array's settling fast and linear, common-centroid layout keeps its binary ratios accurate, and the array itself elegantly serves as both the converter's sample-and-hold and its digital-to-analog core simultaneously. It is a reminder that a circuit block's own internal weaknesses are frequently just the same fundamental problems this series has already solved elsewhere, reappearing in a new physical location rather than demanding an entirely new technique to fix.