CESL contact etch stop liner
**Contact Etch Stop Liner (CESL) and Stress Liners** are the **thin silicon nitride films deposited over the transistor structure that serve dual functions: as etch stop layers for contact hole formation and as uniaxial stress sources to enhance carrier mobility** — with tensile SiN boosting NMOS electron mobility and compressive SiN boosting PMOS hole mobility through the dual stress liner (DSL) integration scheme.
**CESL as Etch Stop**: During contact (via) formation, the etch process must penetrate through the interlayer dielectric (SiO₂/SiOCH) and stop precisely on the silicide surface of the source/drain or gate. The CESL provides high etch selectivity (SiO₂:SiN > 10:1 in fluorocarbon plasma), preventing punch-through into the transistor structure and accommodating non-uniform contact depths (contacts to gate are shorter than contacts to S/D on the same wafer plane).
**CESL as Stress Source**: PECVD silicon nitride can be deposited with controlled intrinsic stress: **tensile SiN** (deposited at lower temperature, higher NH₃/SiH₄ ratio, UV cure) achieves +1.0-1.7 GPa stress, transferring tensile strain to the underlying NMOS channel (boosting electron mobility by 10-20%); **compressive SiN** (deposited at higher RF power, lower temperature, higher SiH₄ flow) achieves -2.0-3.0 GPa stress, transferring compressive strain to the PMOS channel (boosting hole mobility by 15-30%).
**Dual Stress Liner (DSL) Integration**:
| Step | Process | Purpose |
|------|---------|--------|
| 1. Deposit tensile SiN | Blanket PECVD (full wafer) | NMOS mobility boost |
| 2. Mask NMOS regions | Photolithography | Protect tensile liner over NMOS |
| 3. Etch PMOS regions | Remove tensile SiN from PMOS areas | Clear for compressive liner |
| 4. Deposit compressive SiN | Blanket PECVD | PMOS mobility boost |
| 5. Mask PMOS regions | Photolithography | Protect compressive liner |
| 6. Etch NMOS regions | Remove compressive SiN from NMOS areas | Leave only tensile over NMOS |
**Stress Transfer Mechanics**: The strained SiN liner wraps conformally over the gate and source/drain regions. Due to the geometric constraint (the liner pushes or pulls on the channel through the gate sidewalls and S/D surfaces), the channel experiences uniaxial strain along the current flow direction. The strain magnitude depends on: liner thickness (thicker = more strain), liner stress level (GPa), proximity (closer to channel = more effective), and geometry (fin vs. planar affects stress coupling).
**Stress Engineering at FinFET Nodes**: The transition to FinFET reduced CESL stress effectiveness because: the liner covers the top and sides of the fin, and the stress components partially cancel due to the 3D geometry. Compensating approach: higher-stress liners (>2 GPa), stress memorization technique (SMT — stress imprint from a sacrificial liner that survives anneal), and increased reliance on embedded S/D epi (SiGe, SiC:P) as the primary stressor.
**CESL Thickness Scaling**: As contacted poly pitch (CPP) shrinks, the space available for CESL between adjacent gates decreases. Thick CESL creates void-fill challenges in the narrow gaps. Solution: thin the CESL (20-30nm vs. 50-80nm at older nodes) and compensate with higher intrinsic stress per unit thickness, or defer more strain duty to the S/D epi stressor.
**CESL and stress liners exemplify the elegant multi-functionality of CMOS process films — a single deposition step that simultaneously provides critical etch selectivity for contact formation and meaningful performance enhancement through strain engineering, demonstrating how every layer in the process stack is optimized for maximum impact.**