dual stress liner
**Dual Stress Liner (DSL)** is the **technique of depositing different stress-type silicon nitride films over NMOS and PMOS transistors** — applying tensile stress over NMOS to boost electron mobility and compressive stress over PMOS to boost hole mobility, providing 10-20% drive current improvement at technology nodes from 90nm through 28nm.
**Stress-Mobility Relationship**
- **NMOS**: Tensile stress along channel direction enhances electron mobility.
- Mechanism: Tensile strain splits conduction band valleys, reducing effective mass and inter-valley scattering.
- Improvement: 10-15% Idsat increase from tensile SiN liner.
- **PMOS**: Compressive stress along channel direction enhances hole mobility.
- Mechanism: Compressive strain lifts light-hole band degeneracy, reducing effective mass.
- Improvement: 15-25% Idsat increase from compressive SiN liner + embedded SiGe S/D.
**DSL Process Flow**
1. **Deposit tensile SiN**: PECVD SiN at high UV cure power → tensile stress ~1.5-2.0 GPa. Blanket over entire wafer.
2. **Mask PMOS**: Photoresist covers PMOS regions.
3. **Etch NMOS liner away from PMOS**: Remove tensile SiN over PMOS.
4. **Strip resist**.
5. **Deposit compressive SiN**: PECVD SiN at high RF power → compressive stress ~ -2.0 to -3.0 GPa.
6. **Mask NMOS**: Photoresist covers NMOS regions.
7. **Etch PMOS liner away from NMOS**: Remove compressive SiN over NMOS.
8. **Strip resist**.
**Result**: Each transistor type has its optimal stress liner.
**CESL (Contact Etch Stop Liner)**
- The stress liner also serves as the etch stop layer for the contact etch.
- Contact etch through ILD oxide stops on the SiN liner → opens selectively to expose S/D and gate.
- Dual function: Stress engineering + etch stop.
**Stress Liner Parameters**
| Parameter | Tensile SiN | Compressive SiN |
|-----------|------------|------------------|
| Stress | +1.5 to +2.0 GPa | -2.0 to -3.0 GPa |
| Deposition | PECVD + UV cure | PECVD (high RF power) |
| Thickness | 40-80 nm | 40-80 nm |
| Target Device | NMOS | PMOS |
**Evolution**
- **90nm**: Single stress liner introduced (tensile SiN for NMOS).
- **65-45nm**: DSL mainstream — both tensile and compressive liners.
- **32-28nm**: DSL combined with embedded SiGe S/D for PMOS.
- **14nm+** (FinFET): Liner stress less effective on 3D fins — replaced by channel SiGe and other strain sources.
Dual stress liner was **a key mobility enhancement technique during the planar CMOS era** — providing cost-effective performance improvement through strategic mechanical stress engineering that squeezed maximum carrier velocity from silicon channels before the transition to FinFET architecture.