tensile stress

Tensile stress in CVD thin films refers to an intrinsic mechanical stress state where the deposited film tends to contract or pull inward relative to the substrate, creating a condition where the film is under tension. If the film could freely contract, it would occupy less area than the substrate surface it covers; since it is constrained by adhesion to the rigid substrate, the film remains in a state of biaxial tensile stress. This is the opposite of compressive stress, where the film would tend to expand. Tensile stress in CVD films can lead to several critical failure modes including film cracking (when tensile stress exceeds the fracture strength), delamination at weak interfaces, wafer bowing (the wafer curves concavely toward the film side), and device performance degradation through strain-induced mobility changes in underlying transistors. The magnitude and sign of film stress depend on deposition conditions, chemistry, film composition, and post-deposition thermal history. In PECVD silicon nitride, stress can be tuned from highly compressive (~-3 GPa) to highly tensile (~+1.5 GPa) by adjusting RF frequency, power, pressure, gas ratio, and temperature. Low-frequency PECVD typically produces compressive films due to increased ion bombardment, while high-frequency deposition tends toward tensile stress. This tunability is explicitly exploited in stress engineering for advanced transistors — tensile silicon nitride films deposited as contact etch stop layers (CESL) over NMOS transistors enhance electron mobility through tensile channel strain, improving drive current by 10-15%. Film stress is measured using wafer bow techniques based on Stoney's equation, where the curvature change of the wafer before and after film deposition is related to the film stress through the substrate mechanical properties and film thickness. Laser-based wafer curvature measurement systems provide whole-wafer stress maps. Stress management in multi-layer film stacks is critical to prevent cumulative stress from exceeding adhesion strength or causing excessive wafer distortion that impacts lithographic overlay alignment.