epitaxial source drain strain

**Epitaxial Source/Drain Strain Engineering** is **the technique of growing lattice-mismatched crystalline semiconductor materials in transistor source and drain regions to induce uniaxial stress in the channel, enhancing carrier mobility by 30-80% and enabling continued performance scaling without aggressive gate length reduction at advanced CMOS nodes**. **Strain Engineering Fundamentals:** - **Compressive Stress for PMOS**: SiGe epitaxy in S/D regions (Ge 25-45%) creates compressive uniaxial stress of 1-3 GPa in the channel, increasing hole mobility by 50-80% - **Tensile Stress for NMOS**: Si:C (carbon 1-2.5%) or Si:P (phosphorus >2×10²¹ cm⁻³) S/D epitaxy induces tensile channel stress, boosting electron mobility by 30-50% - **Stress Transfer Mechanism**: lattice mismatch between epi S/D and Si channel creates strain field—closer proximity of S/D to channel (shorter Lg) amplifies stress transfer efficiency - **Piezoresistance Coefficients**: hole mobility enhancement in <110> channel under compressive stress is ~71.8×10⁻¹² Pa⁻¹; electron mobility enhancement under tensile stress is ~31.2×10⁻¹² Pa⁻¹ **SiGe S/D Epitaxial Growth (PMOS):** - **Recess Etch**: sigma-shaped or U-shaped S/D cavities etched using NH₄OH-based wet etch or Cl₂/HBr dry etch to maximize stress proximity—sigma shape with {111} facets positions SiGe tip within 5-8 nm of channel - **Growth Chemistry**: SiH₂Cl₂ + GeH₄ + HCl + B₂H₆ at 600-700°C and 10-20 Torr in RPCVD chamber - **Ge Grading**: multi-layer structure with increasing Ge content (e.g., 25% seed / 35% bulk / 45% cap) manages strain relaxation and maximizes channel stress - **Boron Doping**: in-situ B doping at 2-5×10²⁰ cm⁻³ in lower region graded to >2×10²¹ cm⁻³ at surface for low contact resistance - **Selective Growth**: HCl co-flow at 50-200 sccm etches nuclei on dielectric surfaces while preserving epitaxial growth on Si—selectivity window requires precise HCl/SiH₂Cl₂ ratio **Si:P S/D Epitaxial Growth (NMOS):** - **Phosphorus Incorporation**: metastable P concentrations of 2-5×10²¹ cm⁻³ achieved through low-temperature epitaxy (450-600°C) using SiH₄ + PH₃ chemistry - **Active P Challenge**: only 50-70% of incorporated P atoms occupy substitutional lattice sites—remainder are electrically inactive interstitials or clusters - **Millisecond Anneal**: nanosecond or millisecond laser annealing at 1100-1300°C surface temperature activates >90% of P while preventing diffusion (diffusion length <1 nm) - **Surface Morphology**: high P concentration degrades surface roughness to 0.5-1.0 nm RMS—requires growth rate optimization below 5 nm/min **Advanced Node Considerations:** - **FinFET S/D Merging**: merged epitaxial S/D between adjacent fins increases total S/D volume and stress—inter-fin spacing of 25-30 nm at N5/N3 requires precise growth coalescence control - **Nanosheet S/D Formation**: inner spacer defines S/D epi interface with channel—epi must grow selectively from exposed Si nanosheet edges without bridging between sheets - **Wrap-Around Contact (WAC)**: S/D epi shape engineered to maximize contact area with wrap-around metal contact, reducing parasitic resistance by 20-30% - **Defect Management**: stacking faults and twin boundaries in high-Ge SiGe compromise junction leakage—defect density must be below 10⁴ cm⁻² for yield targets **Epitaxial source/drain strain engineering continues to be one of the most effective performance boosters in the CMOS toolkit, contributing up to 40% of the total drive current improvement at each new technology node and remaining essential for both FinFET and nanosheet gate-all-around transistor architectures through the 2 nm generation and beyond.**