boron doped sige
**Boron-Doped SiGe (B:SiGe) for PMOS Source/Drain** is the **in-situ doped epitaxial material grown in the source/drain regions of PMOS transistors that simultaneously provides compressive channel strain for hole mobility enhancement and heavy boron doping for low contact resistance** — where the germanium concentration (25-60 at%), boron doping level (1-5 × 10²⁰/cm³), and epitaxial layer geometry are precisely engineered to maximize PMOS drive current while maintaining crystal quality and avoiding relaxation defects.
**Why B:SiGe for PMOS**
- Silicon channel: Hole mobility is ~2.5× lower than electron mobility → PMOS is inherently slower.
- Compressive strain: SiGe has larger lattice than Si → compressed channel → splits valence band → 40-60% mobility boost.
- Higher Ge%: More strain → more mobility gain, but risk of relaxation defects.
- In-situ boron: Eliminates S/D implant step → junction abruptness → lower resistance.
**B:SiGe S/D Process Flow**
1. **S/D recess etch**: Remove Si from S/D regions (typically 30-60nm deep).
2. **Pre-epitaxy clean**: HF + H₂ bake → remove native oxide from recess.
3. **SiGe nucleation**: Thin undoped SiGe buffer → smooth interface.
4. **B:SiGe growth**: Main stressor layer with target Ge% and B doping.
5. **Optional Si cap**: Thin Si layer for silicide contact formation.
**Ge Content and Strain**
| Ge Content | Lattice Mismatch | Channel Strain | Mobility Gain | Risk |
|-----------|-----------------|---------------|--------------|------|
| 25% | 1.0% | Moderate | ~25% | Low |
| 35% | 1.4% | High | ~40% | Medium |
| 45% | 1.8% | Very high | ~55% | Higher |
| 60% | 2.5% | Maximum | ~70% | Relaxation risk |
**Boron Doping**
- Target: 1-5 × 10²⁰ /cm³ (extremely high → metallic-like conductivity).
- In-situ: B₂H₆ or BCl₃ co-flowed during epitaxial growth → incorporated during crystal formation.
- Advantages over implant: No implant damage, atomically abrupt junction, no need for activation anneal.
- Challenge: High B concentration depresses growth rate → recipe adjustment needed.
- B segregation: B tends to segregate to surface → graded doping profile.
**Epitaxy Challenges**
| Challenge | Cause | Mitigation |
|-----------|-------|------------|
| Relaxation | Exceeding critical thickness at high Ge% | Multi-step Ge grading |
| Dislocations | Lattice mismatch strain relief | Optimize recess geometry |
| Ge non-uniformity | Gas depletion, loading effects | Multi-zone gas delivery |
| Faceting | Crystal-orientation-dependent growth | Temperature/pressure tuning |
| Boron out-diffusion | Later thermal steps diffuse B | Minimize thermal budget |
| Pattern-dependent growth | Dense vs. isolated features grow differently | Dummy pattern insertion |
**FinFET/GAA Specific Considerations**
- FinFET: S/D epi grows from narrow fin → diamond-shaped cross-section.
- Merged fins: Adjacent fins' epi merges → larger contact area → lower resistance.
- GAA nanosheet: Epi wraps around multiple sheets → complex 3D growth.
- Higher Ge at top: Graded Ge profile → more strain closer to channel.
Boron-doped SiGe source/drain epitaxy is **the single most impactful PMOS performance enhancement in modern CMOS technology** — by combining strain engineering (Ge content), doping engineering (in-situ B), and geometric optimization (recess depth and shape) in one process step, B:SiGe S/D delivers the 40-60% PMOS mobility improvement that closes the gap with NMOS performance and enables the balanced circuit speeds required for competitive logic products at every node from 22nm through 2nm and beyond.