source drain epitaxy process

**Source/Drain Epitaxy** is the **CMOS process step that grows crystalline semiconductor material in the source and drain cavities adjacent to the transistor channel — using selective epitaxial growth (SEG) to deposit strain-engineered SiGe (for PMOS) or Si:P/Si:C (for NMOS) that simultaneously forms the electrical contact regions and applies beneficial mechanical stress to the channel, boosting carrier mobility by 30-60% and serving as the primary performance enhancement technique from the 90nm node through GAA nanosheets**. **Why Epitaxial Source/Drain** Two simultaneous benefits: (1) **Strain engineering** — the lattice mismatch between the epitaxial material and the silicon channel creates compressive stress (SiGe → PMOS) or tensile stress (Si:C → NMOS) that modifies the silicon band structure, increasing carrier velocity without scaling the gate length. (2) **Low contact resistance** — heavily doped epitaxy (>1×10²¹ cm⁻³) with controlled facets provides lower contact resistance than ion-implanted source/drain. **PMOS: SiGe Source/Drain** SiGe has a larger lattice constant than Si. When grown epitaxially on Si, the SiGe is compressed to match the Si lattice, but it pushes back on the channel with compressive stress — ideal for PMOS because compressive stress increases hole mobility. 1. **Recess Etch**: Dry + wet etch removes silicon in the source/drain region, creating a cavity. The cavity shape (sigma or diamond-shaped) is engineered to maximize stress transfer to the channel. 2. **SEG Growth**: RPCVD (Reduced Pressure CVD) at 550-650°C deposits SiGe with precise Ge content (25-60 atomic %, increasing with each node). Boron is doped in-situ to >5×10²⁰ cm⁻³. 3. **Multi-Layer Stack**: Typical recipe: thin Si seed → graded SiGe buffer → high-Ge SiGe stressor → Si cap. The stack profile is optimized for both stress and contact resistance. **NMOS: Si:P Source/Drain** Phosphorus-doped silicon (or Si:C with 1-2% carbon) provides tensile stress for NMOS electron mobility enhancement. 1. **Selective Growth**: Si:P is grown with in-situ phosphorus doping to concentrations approaching the solid solubility limit (~5×10²¹ cm⁻³ at 600°C). Higher P concentration reduces contact resistance. 2. **Metastable Doping**: P concentrations above equilibrium solubility are achieved using low-temperature epitaxy that kinetically traps P atoms in substitutional sites. Subsequent thermal budget must be minimized to prevent P deactivation (precipitation). **FinFET and GAA Considerations** For FinFETs, source/drain epitaxy grows on the exposed fin sidewalls and top after the fins are recessed. The epitaxial shape must merge between adjacent fins while avoiding excessive faceting that creates voids. For GAA nanosheets, the source/drain epitaxy must contact the edges of each stacked nanosheet. The epitaxial growth on multiple, closely-spaced nanosheet edges (separated by inner spacers) requires precise control to avoid inter-sheet voids and ensure uniform contact to all channels. Source/Drain Epitaxy is **the crystal-growth step that simultaneously creates the transistor's electrical terminals and its performance-boosting stress engine** — a single process that delivers two of the most important functions in modern CMOS, proving that in semiconductor manufacturing, the best solutions often accomplish multiple objectives at once.