source drain epitaxy

**Source/Drain Epitaxy in Advanced CMOS** is the **selective epitaxial growth process that deposits precisely doped semiconductor material (SiGe for PMOS, Si:P or Si:C for NMOS) in the source/drain regions of the transistor — simultaneously providing the heavily doped contact regions for current flow, the mechanical strain that enhances carrier mobility, and the geometric profile that controls short-channel effects, making source/drain epitaxy one of the most multi-functional and tightly controlled process steps in the entire CMOS flow**. **Why Epitaxy for Source/Drain** At the 22nm FinFET node and beyond, simple ion implantation cannot adequately form source/drain junctions: - **3D Geometry**: FinFET and nanosheet channels are 3D structures. Conformal doping by implantation into vertical fins or wrapped nanosheets is geometrically impossible without unacceptable damage. - **Strain Engineering**: Epitaxially grown SiGe (PMOS) and Si:C (NMOS) in the source/drain regions provide channel stress — the single most effective mobility enhancement technique. - **Contact Area**: Epi merges adjacent fins and provides a large, flat top surface for contact landing. Without epi, each fin would require an individual contact — impossibly small at advanced nodes. **PMOS Source/Drain: SiGe Epitaxy** - **Material**: Si₁₋ₓGeₓ with x = 0.30-0.65. Higher Ge content provides more compressive stress but increases defect risk (lattice mismatch >2%). - **In-Situ Boron Doping**: Boron is incorporated during growth at concentrations of 3-8×10²⁰ cm⁻³. In-situ doping avoids the crystal damage of implantation and activates immediately. - **sigma profile**: Diamond-shaped or hexagonal cross-section controlled by crystal faceting on {111} planes during selective growth. The sigma shape maximizes stressed volume near the channel. - **Multi-Layer Growth**: Graded SiGe (low Ge → high Ge → capping Si) manages strain relaxation and provides a defect-free high-Ge layer close to the channel where strain matters most. **NMOS Source/Drain: Si:P Epitaxy** - **Material**: Silicon with in-situ phosphorus doping at 2-5×10²¹ cm⁻³ (metastable concentrations exceeding solid solubility achieved by low-temperature epitaxy). - **Si:C Option**: Carbon substitutionally incorporated at 1-2 atomic% creates tensile strain for NMOS mobility enhancement. Limited C incorporation makes this less impactful than SiGe for PMOS. - **Challenge**: Phosphorus deactivation during subsequent thermal processing. Ultra-low temperature millisecond anneal preserves the metastable active P concentration. **Selectivity** The epitaxy must grow only on exposed silicon (in source/drain cavities) and NOT on the oxide/nitride isolation and gate spacer surfaces. Selective growth is achieved by adding HCl to the growth chemistry — HCl etches polycrystalline nuclei on dielectric surfaces faster than epitaxial growth proceeds on single-crystal silicon. The etch/growth balance is controlled by HCl flow, temperature (550-700°C), and precursor partial pressures. **Nanosheet-Specific Challenges** In gate-all-around nanosheet FETs, source/drain epitaxy must grow from the exposed nanosheet sidewalls, merging between stacked sheets to form a continuous source/drain region that provides both contact area and channel strain. The inner spacer recess depth critically controls the epi growth front and stress transfer. Source/Drain Epitaxy is **the multi-purpose process step that delivers doping, strain, and contact geometry in a single growth operation** — engineering the three-dimensional semiconductor crystal that feeds current into the transistor channel and determines both performance and manufacturability at every advanced node.