selective epitaxy process
**Selective Epitaxy and Raised Source/Drain** — Precision crystal growth techniques that deposit semiconductor material exclusively on exposed silicon surfaces while suppressing nucleation on dielectric regions, enabling three-dimensional source/drain architectures that reduce parasitic resistance and improve transistor performance.
**Selective Growth Mechanisms** — Selectivity in epitaxial deposition relies on the differential nucleation behavior between crystalline silicon and amorphous dielectric surfaces. On silicon, incoming precursor molecules find energetically favorable lattice sites for ordered crystal growth, while on oxide or nitride surfaces, nucleation requires higher supersaturation to form stable clusters. Adding HCl etchant gas to the deposition chemistry preferentially removes poorly bonded nuclei on dielectric surfaces while minimally affecting the faster-growing epitaxial film on silicon. The selectivity window is defined by the temperature, pressure, and HCl/precursor ratio — typical conditions of 600–750°C, 10–80 Torr, and HCl/DCS ratios of 1–3 achieve selectivity exceeding 50:1 for practical deposition thicknesses of 20–60nm.
**Raised Source/Drain Architecture** — Raised source/drain (RSD) structures deposit 15–40nm of epitaxial silicon above the original substrate surface in the source/drain regions, providing additional silicon volume for silicide formation without consuming junction depth. This architecture is particularly valuable for ultra-thin body SOI and FinFET devices where the limited silicon thickness constrains silicide thickness and increases contact resistance. In-situ doping during RSD growth with phosphorus (NMOS) or boron (PMOS) at concentrations of 1–3×10²⁰ cm⁻³ creates low-resistance source/drain extensions without the lattice damage and transient enhanced diffusion associated with ion implantation.
**Faceting and Morphology Control** — Epitaxial growth on patterned substrates produces crystallographic facets along low-energy planes, with {111}, {311}, and {100} facets appearing depending on growth conditions and pattern geometry. Facet formation reduces the effective raised height at pattern edges and creates non-uniform thickness profiles that impact subsequent silicide and contact formation. Low-temperature growth (550–650°C) with cyclic deposition-etch sequences suppresses faceting by operating in a kinetically limited regime where surface diffusion is insufficient for equilibrium facet development. Pattern-dependent loading effects cause growth rate variations of 5–15% between isolated and dense features — recipe optimization with adjusted deposition time or multi-step processes compensates for loading-induced thickness non-uniformity.
**Defect Management** — Stacking faults, twin boundaries, and misfit dislocations in epitaxial films originate from surface contamination, incomplete native oxide removal, or strain relaxation in lattice-mismatched systems. Pre-epitaxy surface preparation using HF-last cleaning followed by in-situ hydrogen bake at 800–850°C removes native oxide and carbon contamination to below detection limits. For SiGe epitaxy, maintaining film thickness below the critical thickness for the given germanium concentration prevents strain relaxation and associated threading dislocation generation that would increase junction leakage current.
**Selective epitaxy and raised source/drain techniques provide essential design flexibility for managing the competing requirements of shallow junction depth, low sheet resistance, and minimal contact resistance that define source/drain engineering at every advanced CMOS technology node.**