source drain epitaxial growth
**Source/Drain Epitaxial Growth Process** — Precision semiconductor crystal growth technology enabling strain engineering, junction profile optimization, and contact resistance reduction in advanced CMOS transistors.
**Selective Epitaxial Growth Fundamentals** — Source/drain epitaxy employs selective deposition where silicon or silicon-germanium grows only on exposed crystalline silicon surfaces while nucleation on dielectric surfaces is suppressed. Chemical vapor deposition using dichlorosilane (SiH2Cl2) or silane (SiH4) precursors with germane (GeH4) for SiGe and HCl as an etchant gas achieves selectivity ratios exceeding 100:1. Growth temperatures of 550–700°C balance deposition rate, selectivity, and crystalline quality — lower temperatures improve selectivity but reduce throughput and may introduce stacking faults.
**SiGe Epitaxy for PMOS Strain** — Embedded SiGe source/drain regions with germanium concentrations of 25–45% create uniaxial compressive stress in the PMOS channel, enhancing hole mobility by 50–80%. Sigma-shaped recesses etched using TMAH-based wet chemistry maximize the proximity of the SiGe stressor to the channel region. Multi-layer SiGe stacks with graded germanium concentration profiles optimize the trade-off between strain magnitude and defect-free growth — exceeding the critical thickness for a given Ge fraction introduces misfit dislocations that relax the beneficial strain.
**SiC and Si:P Epitaxy for NMOS** — Carbon-doped silicon (Si:C) with 1–2% substitutional carbon creates tensile channel stress for NMOS mobility enhancement, though achieving high substitutional carbon incorporation remains challenging. At advanced nodes, heavily phosphorus-doped silicon epitaxy (Si:P) with concentrations exceeding 3×10²¹ cm⁻³ reduces source/drain sheet resistance and contact resistivity. In-situ phosphorus doping during epitaxial growth provides more abrupt junction profiles than ion implantation approaches.
**Morphology and Faceting Control** — Epitaxial growth on patterned substrates produces faceted surfaces along crystallographic planes, with {111} and {311} facets dominating depending on growth conditions. Facet engineering through temperature and pressure modulation controls the final source/drain shape, which directly impacts the proximity of the stressor to the channel and the available contact landing area. Cyclic deposition-etch processes improve surface planarity and reduce loading effects across varying pattern densities.
**Source/drain epitaxial growth has become indispensable in modern CMOS fabrication, simultaneously delivering channel strain for performance enhancement and enabling ultra-low contact resistance critical for maintaining drive current at aggressively scaled dimensions.**