epitaxial

**Selective Epitaxial Growth (SEG)** is the **site-selective deposition of crystalline Si, SiGe, or SiC on exposed Si surfaces (via Cl-based CVD chemistry) — avoiding nucleation on dielectric — enabling raised source/drain regions with strain-engineering benefits and improved contact resistance at advanced nodes**. SEG is essential for modern FinFET and GAA devices. **Selectivity Mechanism** Selectivity is achieved via HCl or other Cl-containing gas (e.g., SiCl₄) in the CVD chemistry. Cl radicals etch oxide rapidly, preventing nucleation on oxide/nitride surfaces; simultaneously, they suppress etching on Si (or enhance Si growth via self-limiting surface reactions). The result: Si grows on exposed Si windows (within gate-formed recesses or on contacted S/D regions) but not on oxide. Temperature (700-850°C) and pressure are tuned to maintain selectivity window: too-low temperature reduces growth rate, too-high temperature reduces selectivity (oxide etch increases). **Raised Source/Drain for Contact Resistance** Raised S/D epitaxial growth deposits single-crystal Si on the S/D region, creating topography. The raised S/D: (1) increases surface area for metal contact (reduces contact resistance ~20-40%), (2) improves metal coverage (metal fills raised SD better), (3) enables dopant incorporation in-situ (P for n-S/D, B for p-S/D during growth). Raised S/D height is typically 20-50 nm at 28 nm node, increasing to 50-100 nm at 7 nm node for greater benefit. **In-Situ Doped SiGe for PMOS (Compressive Strain)** For p-MOSFET strain engineering, raised S/D is grown as SiGe (not pure Si). SiGe has larger lattice constant than Si (4.66 Å for Ge vs 5.43 Å for Si), causing compressive strain in the Si channel (Si lattice compressed to match SiGe bond lengths). Compressive strain increases hole mobility by 10-30% (magnitude depends on Ge content). In-situ boron doping (B₂H₆ precursor) during SiGe growth dopes the raised S/D p-type, eliminating need for separate implant/anneal. SiGe Ge content is 10-40% (higher Ge increases strain but reduces bandgap, increasing leakage). **In-Situ Doped Si:C for NMOS (Tensile Strain)** For n-MOSFET strain engineering, raised S/D is grown as Si:C (SiC alloy, not Si₃C or pure SiC). Si:C has smaller lattice constant than Si, causing tensile strain in the Si channel. Tensile strain increases electron mobility by 10-25%. In-situ phosphorus doping (PH₃ precursor) during Si:C growth dopes the raised S/D n-type. Si:C carbon content is 0.5-2% (higher C increases strain but increases defect risk). **Faceting Control** During epitaxial growth, crystal facets develop: low-index planes (e.g., {100}, {111}) grow at different rates. If growth is slow enough, high-index facets ({311}, {100}) dominate, leading to faceted surfaces (sawtooth profile). Faceting can cause issues: (1) non-uniform gate dielectric coverage (thin at facet tips), (2) non-uniform doping (facets have different dopant incorporation rates), (3) roughness increases scattering. Faceting is controlled by: (1) growth rate (faster growth favors {100} planes, no faceting), (2) temperature (higher T reduces faceting), (3) HCl concentration (HCl influences facet formation). Modern processes use high growth rate (~10-50 nm/min) and optimized HCl:SiCl₄ ratio to suppress faceting. **Loading Effect and Density Variation** Epitaxy growth rate depends on local environment: dense regions (many Si windows) see competing consumption of precursor gas, reducing growth rate and height; sparse regions (few windows) see higher growth rate per window. This loading effect causes non-uniform raised S/D height across die (1-3x variation from center to edge in worst case). Loading effect is mitigated by: (1) dummy windows added to sparse regions (increase local density), (2) tuned precursor gas flow (excess precursor compensates for competition), (3) chamber pressure/temperature optimization. Modern processes target <20% height variation across die. **Doping Profile and Implant Elimination** In-situ doping during SEG creates raised S/D with incorporated dopants (B for p-S/D, P for n-S/D). This eliminates the need for separate S/D implant on the epitaxial film. However, the dopant profile is not uniform: dopant incorporation rate depends on growth rate (faster growth incorporates less dopant), surface orientation (dopants incorporate differently on {100} vs facets), and facet formation. This dopant non-uniformity (~10-20% variation) is acceptable for most devices but can be problematic for precision analog circuits. **Source/Drain Resistance and Performance** Raised S/D epitaxy improves S/D resistance by: (1) increasing dopant density (in-situ doping at higher concentration than implant), (2) increasing contact area, (3) reducing contact-to-channel resistance (raised S/D extends dopant closer to channel). Combined benefit: S/D specific contact resistance (ρc) reduces ~30-50%, and sheet resistance (Rsh) reduces ~20-40%, directly improving transistor drive current and reducing parasitic delay. **Selectivity Challenges at Advanced Nodes** As oxide thickness reduces (thinner isolation), selectivity becomes harder: Cl-based chemistry etches thinner oxide faster, risking loss of selectivity. Additionally, higher aspect ratio S/D windows (deeper recessed S/D in FinFET) reduce gas diffusion, degrading selectivity at window bottoms. Selectivity is maintained by: (1) lower growth temperature (>800°C too high for thin oxide), (2) optimized HCl concentration, (3) shorter etch time before growth. At 3 nm node, SEG selectivity is reaching limits, driving research into alternative processes (e.g., ion-implant-free raised S/D approaches). **Summary** Selective epitaxial growth is a transformative process, enabling strain-engineered raised S/D with in-situ doping and improved contact resistance. Continued advances in selectivity at aggressive nodes and faceting control will sustain SEG as a core CMOS technology.