source drain recess

**Source/Drain Recess and Epitaxy** is the **process of etching a recess into the source and drain regions and refilling with a strained epitaxial layer** — engineering channel stress to enhance transistor drive current in advanced CMOS nodes. **Why S/D Epitaxy?** - Strained channel: Deformed Si crystal lattice → altered band structure → higher carrier mobility. - PMOS: Compressive strain → higher hole mobility (50–100% improvement). - NMOS: Tensile strain → higher electron mobility. - S/D epitaxy injects stress directly adjacent to the channel — most effective stress location. **PMOS: SiGe S/D Stressor** - SiGe has ~4% larger lattice constant than Si. - Epitaxially grown SiGe in S/D tries to maintain Si lattice spacing → compressively strained SiGe. - Compressive SiGe squeezes channel laterally → compressive channel stress → boosts hole mobility. - Typical: Si0.6Ge0.4 (40% Ge) → ~1 GPa compressive stress in channel. - First deployed: Intel 90nm (2003), now universal. **NMOS: SiC or SiP S/D Stressor** - Si:C (carbon in Si) has smaller lattice constant → tensile stress in channel. - Or n-SiP (Si:P with high P concentration) grown selectively in NMOS S/D. - Less common than SiGe — tensile stress in NMOS also achieved via SMT and SiN capping. **Process Steps** 1. **Recess Etch**: Dry etch (Cl2/HBr) + selective wet etch to create sigma-shape (diamond) recess. - Sigma-shape (anisotropic Si etch along <111> planes) maximizes stress transfer to channel. - Depth: 30–80nm below gate level. 2. **Pre-clean**: Remove native oxide, contaminants (dilute HF). 3. **Selective Epi**: CVD SiGe (DCS + GeH4 + HCl) — grows only on Si, not on dielectrics. 4. **In-Situ Doping**: Boron (PMOS) or phosphorus (NMOS) incorporated during epi growth. - Boron: B2H6 during growth → p+ contact region. - High boron: 1–2 × 10²¹ cm⁻³ for low contact resistance. **FinFET SiGe** - Fin recess: More complex — recess must not undercut gate spacer. - Higher Ge% at leading edge: Intel 14nm → 35% Ge; TSMC 7nm → 45–55% Ge. S/D epitaxy with stressor materials is **the backbone of PMOS performance from 90nm to current-generation FinFET and GAAFET** — without SiGe stressors, PMOS performance would lag NMOS by 3x rather than the near-equal drive currents achieved in modern CMOS.