source drain recessed epitaxy
**Source/Drain Recessed Epitaxy** is the **CMOS fabrication technique where the original silicon in source/drain regions is etched away (recessed) and replaced with selectively grown epitaxial material (SiGe for PMOS, Si:C or Si:P for NMOS)**, introducing uniaxial channel strain that dramatically enhances carrier mobility — a cornerstone mobility enhancement technique used from the 90nm node (Intel) through current GAA nanosheet technology.
**Strain Engineering Principle**: Lattice-mismatched epitaxial material grown adjacent to the channel creates mechanical stress: **SiGe** (larger lattice than Si) in PMOS S/D regions puts the channel under compressive strain, increasing hole mobility by 50-100%. **Si:C** or highly-doped **Si:P** in NMOS S/D regions creates tensile strain (carbon's smaller lattice pulls the silicon), boosting electron mobility by 20-40%.
**Process Flow for Embedded SiGe (e-SiGe) PMOS**:
| Step | Process | Key Parameters |
|------|---------|---------------|
| 1. Recess etch | Anisotropic dry etch + wet clean on exposed S/D | Depth: 30-60nm, sigma facet control |
| 2. Sigma-shaped cavity | Optional: wet etch (TMAH) for sigma-shaped profile | Creates tip close to channel |
| 3. SiGe epitaxy | Selective CVD at 600-700°C (DCS/GeH₄/HCl) | Ge content: 25-40%, uniformity |
| 4. In-situ B doping | Add B₂H₆ during epitaxy | Doping: >1×10²⁰ cm⁻³ |
| 5. SiGe cap | Optional thin Si or SiGe cap for silicide | Contact resistance control |
**Sigma-Shaped Cavity**: Using TMAH (tetramethylammonium hydroxide) or similar anisotropic wet etchant creates a diamond-shaped cavity bounded by {111} crystal planes. The cavity tip approaches very close to the channel (within 5-10nm of the gate edge), maximizing the strain transfer. This sigma-shaped profile is critical for the maximum performance boost — the closer the stressor to the channel, the stronger the strain.
**Selectivity Challenge**: The epitaxy must grow only in the recessed S/D regions (exposed silicon) and not on dielectric surfaces (SiO₂, SiN spacers, STI). Selectivity is achieved using HCl gas in the CVD process, which etches any nuclei that form on non-crystalline surfaces while allowing continued growth on the crystalline Si seed. Selectivity > 100:1 is required — even thin parasitic deposits on spacers cause defectivity and yield loss.
**Advanced Node Considerations**: At GAA nanosheet nodes, S/D epitaxy must fill the space between released nanosheets — a geometry far more complex than planar or FinFET. The epitaxial growth must conformally wrap around the nanosheet ends, merge between sheets, and provide low contact resistance. The merging profile (bottom-up vs. conformal) is controlled by growth conditions and affects both strain transfer and contact resistance.
**Defect Control**: Common defects include: **stacking faults** (from imperfect recess etch surface preparation), **loading effects** (growth rate varies with local pattern density), **Ge composition non-uniformity** (causes threshold voltage variation), and **faceting** (crystallographic orientation-dependent growth rates create non-planar surfaces). Each must be controlled to sub-percent levels across the wafer.
**Source/drain recessed epitaxy transformed CMOS performance engineering — providing the dominant mechanism for mobility enhancement across multiple technology generations and establishing epitaxial strain as an indispensable component of the transistor fabrication toolkit from planar through FinFET to nanosheet architectures.**