strained silicon process
**Strained Silicon** is the **transistor enhancement technique that improves carrier mobility by 20–80% by intentionally stretching or compressing the silicon crystal lattice in the transistor channel region** — enabling performance gains equivalent to 1–2 node generations without any additional lithographic shrink. Strain engineering was introduced by Intel at 90nm (2003) and has remained a core component of every advanced CMOS process since, evolving from biaxial global strain to highly localized uniaxial strain techniques.
**Physics of Strain-Enhanced Mobility**
- **Electrons (NMOS)**: Tensile strain splits the six degenerate conduction band valleys → electrons populate two lower-energy valleys with lower effective mass → higher electron mobility (+20–50%).
- **Holes (PMOS)**: Compressive strain in-plane splits valence band → lighter hole effective mass → higher hole mobility (+50–80%).
- Key metric: Piezoresistance coefficient — describes how stress changes resistivity in silicon.
**Types of Strain**
| Type | Direction | Best For | How Applied |
|------|----------|---------|------------|
| Biaxial tensile | Both in-plane directions | NMOS | Strained Si on relaxed SiGe substrate (global) |
| Uniaxial compressive | Along channel direction only | PMOS | SiGe S/D recessed epitaxy |
| Uniaxial tensile | Along channel direction only | NMOS | Tensile stress liner (SiN) |
**Key Strain Engineering Techniques**
**1. SiGe Source/Drain (Compressive PMOS Strain)**
- Recess S/D regions → grow SiGe epitaxy (larger lattice constant than Si).
- SiGe pushes against channel → compressive uniaxial strain in channel → hole mobility up +50%.
- Intel introduced at 90nm; universally used since.
- Ge fraction: 20–35% in S/D (limited by dislocation generation).
**2. Stress Liner (CESL — Contact Etch Stop Liner)**
- Tensile SiN liner over NMOS → transmits tensile stress to channel → electron mobility up +20%.
- Compressive SiN liner over PMOS (dual stress liner: DSL).
- Deposited by PECVD; stress controlled by deposition conditions (H content, RF power).
- Stress magnitude: 1–2 GPa tensile or compressive.
**3. Stress Memorization Technique (SMT)**
- Deposit tensile nitride cap before gate anneal → cap memorizes stress in polysilicon gate during recrystallization → stress partially transferred to channel.
- Cap removed after anneal → stress retained in gate/channel region.
- Adds +10% NMOS drive current at minimal process cost.
**4. Strained SiGe Channel (PMOS FinFET/Nanosheet)**
- At FinFET nodes: SiGe channel fins (Ge 25–50%) for PMOS → compressive biaxial strain in SiGe → hole mobility 2× vs. Si.
- At nanosheet: Pure Ge or high-Ge SiGe nanosheets for PMOS for maximum hole mobility.
**Strain in FinFET vs. Planar**
- Planar: Large S/D volume → effective stress transfer to channel.
- FinFET: Fin geometry limits volume of stressor material → process must optimize fin aspect ratio for stress transmission.
- Proximity matters: Stressor within 20–30 nm of gate edge for maximum effect.
**Strain Metrology**
- **Raman spectroscopy**: Non-destructive; measures Raman peak shift → 1 cm⁻¹ shift ≈ 250 MPa biaxial stress.
- **Nano-beam electron diffraction (NBED)**: TEM-based; maps strain in individual fins at atomic scale.
- **X-ray diffraction (XRD)**: Measures lattice parameter change → strain in epi layers.
Strained silicon is **one of the most impactful performance innovations in CMOS history** — delivering 30–80% mobility improvement through deliberate crystal deformation rather than transistor scaling, strain engineering remains indispensable at every node from 90nm to 2nm, evolving its implementation from global epi substrates to atomically localized channel stressors in nanosheets.