strain engineering cmos

**Strain Engineering** is **the systematic application of mechanical stress to the silicon channel to modify the crystal lattice and enhance carrier mobility — using process-induced stress from nitride liners, embedded SiGe source/drains, and substrate strain to achieve 20-50% performance improvement or equivalent power reduction without scaling transistor dimensions**. **Strain Physics:** - **Band Structure Modification**: tensile strain along <110> channel direction reduces the conduction band effective mass and splits the six-fold degenerate valleys; electron mobility increases 50-80% at 1GPa tensile stress by reducing intervalley scattering - **Hole Mobility Enhancement**: compressive stress along <110> channel direction lifts heavy-hole/light-hole degeneracy and reduces hole effective mass; hole mobility increases 30-50% at 1.5GPa compressive stress - **Stress Components**: longitudinal stress (along channel) has the strongest mobility impact; transverse stress (perpendicular to channel) has secondary effects; vertical stress (perpendicular to wafer) generally degrades mobility - **Piezoresistance Coefficients**: silicon mobility change Δμ/μ = π·σ where π is the piezoresistance coefficient (π_longitudinal ≈ -30×10⁻¹¹ Pa⁻¹ for electrons, +70×10⁻¹¹ Pa⁻¹ for holes) and σ is stress magnitude **Stress Induction Techniques:** - **Contact Etch Stop Layer (CESL)**: silicon nitride film deposited over source/drain regions after silicide formation; tensile CESL (1-2GPa intrinsic stress) for NMOS induces tensile channel stress; compressive CESL (1.5-2.5GPa) for PMOS induces compressive stress - **Deposition Conditions**: plasma-enhanced CVD (PECVD) at 400-500°C with controlled SiH₄/NH₃/N₂ ratios and RF power; high RF power and low temperature produce high tensile stress; high NH₃ ratio produces compressive stress - **Stress Transfer Efficiency**: stress transfer from CESL to channel depends on gate length, spacer width, and film thickness; shorter gates receive more stress (stress scales as 1/Lgate); typical channel stress 200-500MPa from 1.5GPa CESL film - **Dual Stress Liner (DSL)**: separate tensile and compressive CESL films for NMOS and PMOS; requires block masks to selectively deposit or etch liners; adds two mask layers but provides optimized stress for each device type **Embedded SiGe Source/Drain:** - **PMOS Stress Source**: etch silicon source/drain regions, epitaxially regrow Si₁₋ₓGeₓ with x=0.25-0.40; SiGe has 4% larger lattice constant than Si, creating compressive stress in the channel when constrained by surrounding silicon - **Recess Etch**: anisotropic RIE removes silicon to depth of 40-80nm in source/drain regions; recess shape (sigma, rectangular, or faceted) affects stress magnitude and uniformity; deeper recess provides more stress but increases parasitic resistance - **Selective Epitaxy**: low-temperature epitaxy (550-650°C) using SiH₂Cl₂/GeH₄/HCl chemistry grows SiGe only on exposed silicon, not on dielectric surfaces; in-situ boron doping (1-3×10²⁰ cm⁻³) provides low contact resistance - **Stress Magnitude**: 30% Ge content produces 800-1200MPa compressive channel stress; stress increases with Ge content but higher Ge causes defects and strain relaxation; 25-30% Ge is optimal for 65nm-22nm nodes **Stress Memorization Technique (SMT):** - **Concept**: stress induced in polysilicon gate during high-temperature anneals is "memorized" and transferred to the channel after gate patterning; exploits the stress relaxation behavior of polysilicon vs single-crystal silicon - **Process Flow**: deposit tensile nitride cap over polysilicon gates before source/drain anneals; during 1000-1050°C activation anneal, polysilicon gate expands and induces tensile stress in underlying channel; remove nitride cap after anneal - **Stress Retention**: polysilicon relaxes stress quickly after anneal, but single-crystal channel retains stress due to lower defect density; retained channel stress 50-150MPa provides 5-10% mobility enhancement - **Advantages**: SMT is compatible with gate-first HKMG processes and adds minimal process complexity; provides supplementary stress to CESL and eSiGe techniques **Integration Challenges:** - **Stress Relaxation**: high-temperature processing (>800°C) after stress induction causes partial stress relaxation through dislocation motion; thermal budget management critical to preserve stress - **Pattern Density Effects**: stress magnitude varies with layout density; isolated transistors receive different stress than dense arrays; stress-aware design rules and optical proximity correction (OPC) compensate for layout-dependent stress variations - **Short Channel Effects**: stress can worsen short-channel effects by modifying band structure and barrier heights; careful co-optimization of channel doping, halo implants, and stress magnitude required - **Strain Compatibility**: tensile NMOS stress and compressive PMOS stress require opposite film properties; dual-liner or embedded SiGe approaches add mask layers and process complexity but provide optimal per-device-type stress Strain engineering is **the most cost-effective performance booster in CMOS scaling history — providing 20-50% drive current improvement without shrinking dimensions, enabling multiple technology node generations to meet performance targets while managing power density and leakage constraints**.