stress engineering strain technology

**Stress Engineering and Strain Technology** — Deliberate introduction of mechanical stress into transistor channel regions to enhance carrier mobility and drive current without geometric scaling, serving as a primary performance booster across multiple CMOS technology generations. **Strain Physics and Mobility Enhancement** — Mechanical stress modifies the silicon band structure by splitting degenerate energy valleys and altering effective carrier masses. Uniaxial compressive stress along the <110> channel direction enhances hole mobility by 50–100% through valence band warping and reduced inter-band scattering in PMOS devices. Uniaxial tensile stress enhances electron mobility by 30–50% in NMOS through conduction band splitting that preferentially populates the low-effective-mass Δ2 valleys. The magnitude of mobility enhancement depends on stress level, crystallographic orientation, and channel length — short-channel devices experience higher stress from proximal stressors due to reduced stress relaxation along the channel. **Embedded Stressor Techniques** — Embedded SiGe (eSiGe) source/drain regions with 25–45% germanium concentration create uniaxial compressive stress in PMOS channels through lattice mismatch between the SiGe stressor and silicon channel. Diamond-shaped (sigma) recesses etched using crystallographic wet etch chemistry maximize stressor volume and proximity to the channel. For NMOS, embedded SiC source/drain with 1–2% substitutional carbon provides tensile channel stress, though carbon incorporation challenges limit the achievable stress magnitude. At FinFET nodes, epitaxial stressor effectiveness is modified by the three-dimensional fin geometry — stress transfer efficiency depends on fin width, height, and the stressor-to-channel geometric relationship. **Stress Liner and Memorization Techniques** — Contact etch stop liners (CESL) deposited with intrinsic tensile stress (1.5–2.0 GPa) or compressive stress (2.5–3.5 GPa) transfer stress to the underlying channel through mechanical coupling. Dual stress liner (DSL) integration applies tensile liners over NMOS and compressive liners over PMOS through selective deposition and etch-back processes. Stress memorization technique (SMT) exploits the amorphization and recrystallization sequence during source/drain implant activation — a tensile capping layer present during the recrystallization anneal locks in tensile stress that persists after liner removal, providing NMOS enhancement without permanent liner stress. **Stress Metrology and Simulation** — Nano-beam diffraction (NBD) in transmission electron microscopy measures local strain with spatial resolution below 5nm and strain sensitivity of 0.02%. Raman spectroscopy provides non-destructive stress measurement through stress-induced phonon frequency shifts. Finite element modeling and atomistic simulation predict stress distributions in complex 3D device geometries, guiding stressor design optimization. Process-induced stress interactions between multiple stressor elements (STI, epitaxial S/D, liners, silicide) require holistic simulation to capture the net channel stress accurately. **Stress engineering has delivered cumulative performance improvements equivalent to multiple technology node advances, and remains an essential component of the CMOS performance toolkit as the industry transitions from FinFET to gate-all-around architectures where new stressor geometries must be developed.**