stress memorization technique

**Stress Memorization Technique (SMT)** is a **process technique that uses a stressed capping film deposited over the transistor to permanently memorize tensile stress in the poly gate and channel region** — boosting NMOS drive current by 5–15% without additional process complexity. **Background: Strained Silicon** - Tensile strain in NMOS channel: Lifts Si band degeneracy → reduces effective mass for electrons → increases electron mobility. - Compressive strain in PMOS channel: Improves hole mobility. - Intel introduced strained silicon at 90nm (2003) — became standard across the industry. **SMT Mechanism** 1. Deposit tensile SiN capping layer (stress ~1–1.5 GPa tensile) over poly gate and active region after S/D implant. 2. Perform source/drain activation anneal (spike anneal, 1050°C). 3. During anneal: Poly gate recrystallizes. Tensile film constrains poly from expanding → tensile stress "locked in" via dislocation pinning. 4. Remove SiN capping layer by selective etch. 5. Result: Poly gate retains memorized tensile stress → transmits to underlying channel. **Process Specifics** - SiN stress: 1–1.5 GPa tensile (PECVD, high-frequency mode). - Thickness: 50–100nm — thicker = more stress, but more etch residue risk. - NMOS only: Tensile stress helps electrons; compressive film over PMOS instead. - Anneal time/temperature critical: Too slow → stress relaxes; too fast → incomplete activation. **Benefit** - NMOS Idsat improvement: 5–15%. - No additional photolithography mask. - Stackable with other stress techniques (SiGe S/D, DSL). **Combination with Dual Stress Liner (DSL)** - SMT + DSL: Tensile SiN over NMOS (both techniques), compressive SiN over PMOS. - Each contributes independently → additive mobility enhancement. SMT is **a cost-effective performance booster for NMOS transistors** — widely adopted at 65nm–28nm as an easy enhancement layer that does not require mask additions or major process changes.