stress memorization technique

**Stress Memorization Technique (SMT)** is **a process integration method that permanently transfers tensile stress into the NMOS channel region by depositing a high-stress silicon nitride film over the gate structure, performing a high-temperature anneal to lock the stress into the source/drain and channel lattice through dopant activation and recrystallization, and then removing the nitride stressor film** — delivering significant electron mobility enhancement without requiring the stressor to remain in the final device structure. - **Mechanism**: During source/drain implantation, the silicon lattice is amorphized to a depth determined by implant energy and dose; the highly stressed nitride capping layer constrains the regrowth direction during the subsequent spike or millisecond anneal, causing the silicon to recrystallize with a permanently strained lattice that persists even after the nitride is stripped. - **Tensile Stress Benefit for NMOS**: The memorized tensile strain along the channel direction splits the conduction band degeneracy, lowering the effective electron mass and reducing intervalley scattering; drive current improvements of 10-15 percent for NMOS transistors are routinely achieved at the 45 nm and 32 nm nodes. - **Nitride Film Deposition**: PECVD silicon nitride films with intrinsic tensile stress of 1.0-1.7 GPa are deposited at 400-480 degrees Celsius; film stress is controlled through RF power, gas flow ratios (SiH4/NH3/N2), and chamber pressure, with higher UV cure temperatures producing even higher stress levels. - **Anneal Optimization**: The stress memorization anneal typically coincides with the source/drain activation anneal at temperatures of 1000-1050 degrees Celsius for spike RTA or 1100-1300 degrees Celsius for millisecond laser/flash anneal; the amorphous-to-crystalline transformation must complete under the mechanical constraint of the nitride cap for maximum stress transfer. - **Selective Application**: SMT is applied only to NMOS devices because tensile stress degrades PMOS hole mobility; a masking step protects PMOS regions from the nitride stressor deposition, or a compressive nitride is deposited over PMOS in a dual-stress liner (DSL) scheme that combines SMT and conventional contact etch stop liner (CESL) approaches. - **Process Window**: The amorphization depth, nitride stress level, and anneal conditions must be co-optimized; insufficient amorphization results in weak stress memorization, while excessive amorphization risks incomplete recrystallization and residual defects that increase junction leakage. - **Interaction with Other Stressors**: SMT stress adds to the strain provided by embedded source/drain stressors, STI stress, and metal gate stress; the total channel stress must be managed holistically to avoid over-stressing that can cause dislocation nucleation or crystal defects. SMT represents an elegant process-based strain engineering solution that leverages the existing implant and anneal steps to permanently enhance NMOS performance at minimal additional cost and complexity.