stress engineering cmos

**Stress/Strain Engineering in CMOS** is the **deliberate application of mechanical stress to the transistor channel to modify the silicon crystal band structure and enhance carrier mobility — where compressive stress boosts hole mobility (PMOS) by 40-60% and tensile stress boosts electron mobility (NMOS) by 15-30%, providing performance gains equivalent to one or more technology node shrinks without any dimensional scaling**. **The Physics of Strain-Enhanced Mobility** Mechanical stress distorts the silicon crystal lattice, changing the shape and relative energies of the conduction and valence band valleys. For NMOS (n-type): tensile stress along the channel direction lifts the degeneracy of the six conduction band valleys, populating the two lighter-mass valleys preferentially — reducing the conductivity effective mass and increasing mobility. For PMOS (p-type): compressive stress changes the valence band curvature and reduces inter-band scattering, dramatically increasing hole mobility. **Stressor Techniques** - **Embedded SiGe Source/Drain (PMOS)**: The most powerful PMOS stressor. Etched S/D cavities are filled with epitaxial SiGe (25-50% Ge). Because SiGe has a larger lattice constant than Si, the epitaxial SiGe compresses the channel along its length. Up to 2 GPa of compressive stress is achievable. Introduced by Intel at the 90nm node. - **CESL (Contact Etch Stop Liner)**: A PECVD SiN film deposited over the gate and S/D regions. High-tensile SiN (~1.5 GPa, deposited at high temperature/low plasma power) enhances NMOS. High-compressive SiN (~3 GPa, deposited at low temperature/high plasma power) enhances PMOS. Dual Stress Liner (DSL) uses selective etch to apply different SiN stress to NMOS and PMOS regions. - **Stress Memorization Technique (SMT)**: A high-stress SiN cap is deposited before the S/D activation anneal. During the anneal, the stress from the cap is "memorized" by the recrystallizing silicon (locked in by defect formation). The cap is then removed, but the channel stress remains. Provides ~10-15% NMOS mobility boost. - **SiC Source/Drain (NMOS)**: Epitaxial Si:C (~1-2% carbon) in NMOS S/D creates tensile channel stress. The effect is modest (~10% mobility enhancement) because only a small fraction of carbon substitutes on silicon lattice sites. **Strain in FinFETs and Nanosheets** In FinFET architectures, the 3D geometry modifies how stress is applied and felt by the channel: - **S/D epi stressors** are the dominant strain source — the epitaxial SiGe or SiP grown in the S/D cavities applies longitudinal stress along the fin channel. - **Gate replacement stress**: The metal gate stack applies stress to the channel. Different work-function metals apply different stress levels. - **Nanosheet specifics**: In GAA nanosheets, each stacked sheet is strained by the adjacent S/D epitaxy. The inner spacer geometry affects how effectively the S/D stress transfers to the channel. Stress Engineering is **the free lunch of semiconductor scaling** — delivering performance improvement without shrinking any dimension, by exploiting the quantum-mechanical response of silicon's band structure to mechanical deformation.