cfet
**CFET (Complementary FET)** is an advanced transistor architecture that vertically stacks nFET and pFET devices to dramatically reduce logic cell area beyond FinFET and nanosheet limits.
## What Is CFET?
- **Structure**: pFET stacked directly above nFET (or vice versa)
- **Benefit**: 50%+ area reduction vs. lateral placement
- **Timeline**: Expected at 2nm and beyond (2025+)
- **Challenge**: Complex process integration, thermal budget management
## Why CFET Matters
Horizontal scaling is approaching atomic limits. Vertical stacking provides the next dimension for density improvement.
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**CFET Integration Challenges**:
- Sequential vs. monolithic stacking
- Thermal budget for bottom device
- Contact routing between stacked devices
- Workfunction metal for both polarities