Cfet Logic Distinguish Forksheet as a Transitional Step Before Full Cfet

# CFET (Complementary FET): Step 3 — Distinguish Forksheet as a Transitional Step Before Full CFET

## 1. Why This Distinction Matters Early

`gaa_nanosheet_2020s` Step 11 named forksheet and CFET together as adjacent ideas without separating how far each actually departs from the nanosheet baseline. Before this series goes further into CFET's own integration choices, it is worth drawing that line clearly: forksheet and CFET solve the same underlying problem — a standard cell's n-type and p-type devices taking up too much lateral area — in two structurally different ways, and forksheet is best understood as an intermediate step on the same roadmap rather than a competing end state.

## 2. What Forksheet Actually Changes

A forksheet transistor inserts a single dielectric wall between the n-type and p-type nanosheet stacks of a standard cell, at the exact point where the two device types would otherwise need open space between them for isolation. The wall takes the place of that open space, letting the two stacks sit closer together than unmodified nanosheet GAA allows, while every other unit process — sheet release, inner spacers, conformal gate fill, source/drain epitaxy — stays essentially unchanged from `gaa_nanosheet_2020s` Steps 5-8. It is a single, well-contained structural addition to an already-mature process.

## 3. Why Forksheet Alone Cannot Reach CFET's Area Savings

Even with the dielectric wall closing every bit of lateral gap, forksheet's two devices are still placed side by side in the same plane. The cell's width still has to accommodate both device footprints next to each other; only the isolation gap between them has shrunk, not the device footprints themselves. CFET removes an entire device footprint from the cell's width by moving one device onto a second vertical level instead of compressing the gap between two devices on the same level — a qualitatively larger area reduction that no amount of further lateral wall-thinning can match.

## 4. Forksheet as a Deliberate Intermediate Step

Several foundries have described forksheet publicly as a node-over-node bridge: a way to capture meaningful additional cell-area reduction using nanosheet GAA's existing unit processes, before committing to CFET's much larger integration overhaul (Steps 5-7 of this series). That makes forksheet a transitional technology in the literal sense — it is expected to see production use, if it does, specifically in the window between nanosheet GAA's current maturity and CFET's eventual readiness, not as CFET's permanent replacement or a dead end unrelated to it.

Forksheet Narrows the Gap; CFET Removes a Dimension top-down view of standard-cell width across three architectures nanosheet GAA: wide open-space isolation gap forksheet: dielectric wall, narrower gap, still 2 footprints wide forksheet shrinks the gap between two footprints; CFET removes one footprint from the width entirely this is why forksheet caps out well before CFET's potential area savings
A Roadmap Bridge, Not a Fork in the Road forksheet's expected place between nanosheet GAA and CFET NANOSHEET GAA mature baseline FORKSHEET transitional bridge, reuses existing unit processes CFET full vertical stack, larger integration overhaul forksheet is a deliberate stopping point on the way to CFET, not a permanent alternative to it

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