Cfet Logic Weigh Monolithic Cfet Integration One Continuous Fabrication Sequence

# CFET (Complementary FET): Step 4 — Weigh Monolithic CFET Integration: One Continuous Fabrication Sequence

## 1. The Monolithic Approach, Defined

Monolithic CFET builds the bottom device and the top device on a single wafer, in one continuous epitaxial and fabrication sequence, without ever removing the wafer from the line and bonding it to anything else. The bottom NMOS stack is grown, patterned, and partially processed; the PMOS stack is then grown directly on top of it, in the same chamber sequence, before the full stack is released, gated, and contacted together. Structurally, it is the most direct extension of nanosheet GAA's own approach — grow a superlattice, pattern it, release it — just with twice as many layers and two device types in the same column.

## 2. Why Alignment Is Easy Here

Because both devices are built on the same wafer without ever being physically separated, the top device's features are patterned using the same lithography reference points as the bottom device's — there is no second wafer to align to the first, and no bonding interface whose placement tolerance has to be budgeted into the design rules. This is monolithic CFET's clearest advantage over the sequential alternative (Step 5): whatever alignment precision a single lithography tool chain already delivers for a single wafer, monolithic CFET gets for free across both device levels.

## 3. The Thermal Budget Problem

The decisive drawback is thermal. Growing, activating dopants in, and annealing the top PMOS device happens after the bottom NMOS device already exists on the same wafer — every high-temperature step the top device needs is also, unavoidably, a high-temperature step applied to the already-built bottom device. If the bottom device's junctions, strain profile, or gate-stack materials cannot tolerate the top device's required process temperatures without degrading, the bottom device's performance is compromised by the time the whole stack is finished. This shared thermal budget is monolithic CFET's central engineering constraint, and it drives much of the materials and process-sequencing research specific to this integration path.

## 4. Where Monolithic Integration Is Expected to Matter Most

Because monolithic CFET keeps everything on one wafer, it is generally viewed in the research literature as the lower-cost, higher-throughput path if the thermal budget problem can be solved with low-temperature-compatible processes for the top device — new gate-stack chemistries, lower-temperature anneals, or device architectures more tolerant of a constrained thermal window. This series does not assert that problem as solved; it remains an active area of materials research, discussed further in Step 6's comparison against the sequential alternative.

Monolithic CFET: One Wafer, One Continuous Sequence process flow and the shared thermal budget it creates grow NMOS stack grow PMOS stack on top release, gate, contact both all on the same wafer, same lithography reference frame throughout every top-device high-temperature step also heats the already-built bottom device easy alignment, shared thermal budget — monolithic CFET's central tradeoff
Monolithic's Ledger one advantage, one open research problem ADVANTAGE single-wafer alignment precision, no bonding interface tolerance to budget for OPEN PROBLEM shared thermal budget: top-device processing risks degrading the already-built bottom device Step 6 weighs this directly against sequential CFET's own distinct tradeoff

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