Charge Pump Design
# Charge Pump Design
A chip's supply rail often isn't high enough for everything the chip needs to do. DRAM wordline drivers need a boosted voltage above VDD to pass a full logic high through an access transistor without losing a threshold-voltage drop; flash memory needs an even higher voltage to force electrons through a tunnel oxide during programming. A charge pump builds that higher voltage out of nothing but switches and capacitors — no inductor, no transformer, no separate high-voltage supply rail — by repeatedly shuttling charge from a lower-voltage node to a higher one in small, cumulative steps.
The Dickson charge pump, the classic architecture, stacks diode-capacitor stages so each clock cycle pushes charge one notch higher. Each stage consists of a capacitor coupled to a clock signal and a diode (or a diode-connected transistor in a CMOS implementation) that only lets charge flow forward, toward the next stage. As the clock toggles, each stage's capacitor gets pumped up by roughly one clock swing above the voltage sitting on it already, and the diode prevents that boosted charge from flowing back toward the lower-voltage stage behind it. Cascade enough stages and the output climbs stage by stage, each one adding roughly one clock-amplitude increment, until the final stage delivers a voltage well above VDD using nothing but switching and charge redistribution.
Output current capability, not just output voltage, is the real design constraint, and it drops sharply as voltage gain climbs. Each stage's capacitor can only deliver the charge it stored during the previous clock phase, so a charge pump's maximum output current is set directly by capacitor size, clock frequency, and the number of stages — pushing for a higher output voltage by adding more stages reduces the output current available at that voltage, because the same finite charge now has to satisfy a longer chain of stages before it reaches the output. This tradeoff is why charge pumps work well for low-current, high-voltage applications like DRAM wordline boost or flash programming voltage — loads that need voltage headroom but not much current — and poorly for anything resembling a main logic supply, where an inductor-based switching regulator's much higher current capability is the only practical choice.
Clock-feedthrough and charge-injection noise, the same mechanisms covered elsewhere in this walkthrough's analog-noise material, ripple directly into a charge pump's output. Every stage's capacitor is driven by a hard clock edge, and the parasitic coupling between that clock and the pump's internal nodes injects noise onto the output rail at the clock frequency and its harmonics — a cleaner concern for a digital supply than for a sensitive analog or RF circuit sharing the same die, which is why charge-pump-generated rails almost always get their own downstream regulation or filtering rather than feeding a noise-sensitive load directly. Production DRAM and flash designs at memory makers like SK Hynix, Samsung, and Micron size pump stage count, capacitor area, and clock frequency together as one coupled optimization against the specific current and ripple budget each boosted rail actually needs.
LDO dropout voltage (565) describes a regulator that can only step a supply down, never up, and needs headroom to do even that. Charge pump design solves the opposite problem — generating a voltage higher than anything already available on the chip — using switching and capacitors instead of an inductor, which is exactly what makes it practical to build directly on a memory die without a separate high-voltage supply pin.