charged device model protection

Charged Device Model testing addresses a failure mode that looks nothing like a Human Body Model or Machine Model event: the device under test is never touched by an external charged source at all. Instead, the package itself accumulates charge during ordinary handling, through triboelectric contact with a shipping tube or through field induction on an automated line, and that charge sits stored across the package-to-ground capacitance until a single pin happens to touch a grounded surface. At that instant the entire stored charge exits through that one pin in a fraction of a nanosecond, producing a current density at the discharge site that can exceed what either HBM or Machine Model testing ever applies to a single node. **A CDM event begins with charge storage across the package body and ends with a discharge so fast that the whole transient resolves in about 1 ns to 2 ns once contact occurs.** Charging can happen by direct field induction, where the package sits above a charged plate and pins couple to it capacitively, or by contact and separation against a charged surface such as packaging tape or a tray, both of which are common during automated handling rather than manual touch. Because the charge is stored across the package's own capacitance rather than delivered from an external source through a defined series impedance, the effective source impedance during discharge is extremely low, which is exactly why the resulting current spike is so much sharper than an HBM or Machine Model pulse. **CDM qualification standards group devices into charging-voltage classes, and the classification again uses the highest voltage a part passes rather than an average across samples.** A representative scheme spans Class C1 below 125 V, Class C2 spanning 125 V to 250 V, Class C3 spanning 250 V to 500 V, Class C4 spanning 500 V to 1000 V, and Class C5 above 1000 V, with most modern fine-pitch packages targeting reliable survival somewhere in the C2 to C3 band. Smaller, lower-capacitance packages generally charge to a given voltage with less stored energy than larger packages with more metal layers and larger ground planes, so package selection itself carries CDM risk that a HBM-only qualification plan would never surface. Field-plate charging in a non-socketed test setup is typically stepped in increments near 25 V per level, allowing the exact voltage at which a part first fails to be bracketed with reasonable precision rather than jumping straight from a comfortable pass to catastrophic failure. **The discharge current waveform is a damped oscillation set by the package's own parasitic inductance and capacitance, with peak current typically reached within 0.2 ns to 0.4 ns of first pin contact.** Ring frequency for a typical fine-pitch package commonly falls in the 500 MHz to 900 MHz range, and because that ringing decays within a handful of nanoseconds rather than the hundreds of nanoseconds an HBM pulse takes to decay, the entire energy delivery is compressed into a window roughly two orders of magnitude shorter. This compression is precisely why gate oxide near the discharge pin sees a current density spike that a slower stress event of equal total charge would never reproduce at a single node. Socket or probe contact resistance during the discharge itself commonly falls in the 1 ohm to 5 ohm range, and even that small resistance measurably shapes how sharp the initial current peak appears on a captured waveform. **Pin location and local routing matter more for CDM survivability than for almost any other ESD stress mode, since the discharge path length between pad and protection device directly sets local inductance on a sub-nanosecond time scale.** A corner pin often sees a different local ground return path than a center pin, and even a few mm of extra trace length between a pad and its nearest low-impedance ground point can measurably raise the local voltage overshoot before a clamp fully turns on. Pin-level protection therefore favors compact, fast-triggering diode or clamp structures placed as close to the pad as the pad-ring floorplan allows, trading some area efficiency for a shorter, lower-inductance discharge path. A routing detour of even 2 mm to 3 mm between a corner pad and its nearest ground point can be enough to separate a marginal pass from a marginal fail once every other variable in the layout is held constant. **CDM protection strategy differs from power-rail clamp design because the discharge current in a CDM event often never reaches the main power-rail clamp fast enough to matter.** Local pin-to-rail diodes and small dedicated CDM clamp cells are sized primarily for speed rather than raw current-handling capacity, since their job is to open a low-impedance path within a fraction of a nanosecond rather than sustain current for hundreds of nanoseconds the way an HBM power clamp must. A protection network tuned only against HBM and Machine Model stress can still leave a part with a real CDM weakness, which is why CDM-specific layout review is treated as a separate design step rather than folded into general ESD checks. A CDM clamp cell is typically qualified against a target charging voltage in the 250 V to 500 V band well before a power-rail clamp sized for hundreds of ns of HBM current is finalized, since the two devices are tuned against entirely different portions of the stress time scale. **Correlating CDM results against Very-Fast TLP data gives designers a bench-level tool for predicting CDM robustness without running a full CDM tester on every design iteration, since both stresses operate on a comparable sub-nanosecond to low-nanosecond time scale.** A device that clears VF-TLP at its target current but still fails CDM at an equivalent charging voltage usually points to a package or floorplan parasitic rather than a device-level weakness, since the electrical stress on the protection device itself was already shown adequate under VF-TLP. Field-return failure data consistently shows CDM-related gate-oxide damage concentrated near corner pins and pins with long routing back to their nearest clamp, reinforcing that layout, not just device sizing, determines real-world CDM survival. A part that passes CDM qualification at Class C3 but shows a VF-TLP failure current more than 20% below its sibling design on a different pin is usually flagged for a floorplan review before the next revision is released. **Failure analysis after a CDM overstress event follows the same physical toolchain used across ESD characterization, applied here to a much smaller and more localized damage site.** AFM topography can resolve a rupture footprint measured in tens of nm at the exact pin where discharge occurred, SIMS depth profiling detects any contamination or compositional shift introduced near that site, XPS confirms the chemical state of exposed material after rupture, and DLTS spectroscopy characterizes trap states left behind in the stressed oxide or junction. Because CDM damage is so tightly localized to a single pin, failure analysis teams typically start with the pin nearest the shortest and most direct ground path identified during electrical fault isolation, since that is statistically where the highest local current density occurred. Ring frequency extracted from the captured waveform, often 500 MHz to 900 MHz, is itself a useful diagnostic, since a frequency shift between two otherwise identical parts often points to a package or bond-wire parasitic difference worth investigating before blaming the protection device. | CDM class | Charging voltage range | Typical package risk | Protection implication | |---|---|---|---| | C1 | below 125 V | Low, wide margin | Standard pin-level diodes sufficient | | C2 | 125 V to 250 V | Moderate | Compact fast clamp recommended near pad | | C3 | 250 V to 500 V | Common target band | Short, low-inductance discharge path required | | C4 | 500 V to 1000 V | Elevated | Dedicated CDM clamp cell per pad | | C5 | above 1000 V | High, large packages | Package and floorplan redesign often needed | | Corner pin | package-dependent | Elevated vs center pins | Priority site for failure analysis | ```flowchart Package acquires charge via handling or field induction → Charge stored across package-to-ground capacitance → Pin contacts a grounded surface → Full package charge discharges through that single pin → Peak current reached within 0.2 ns to 0.4 ns → Damped oscillatory ringdown completes within a few ns → Local oxide stress concentrated at the discharge pin → Pin-level clamp must shunt current before oxide ruptures → Failure analysis confirms protection margin (AFM, SIMS, XPS, DLTS) ``` Viewed through a package-level ESD threat engineering lens, the Charged Device Model reframes ESD protection as a floorplan and packaging problem as much as a device problem: the charge is already on the part before any external source ever touches it, the discharge path is set by pin location and local routing rather than a shared external network, and the entire destructive event is over before a power-rail clamp built for HBM or Machine Model time scales could ever respond, which is exactly why pin-level, sub-nanosecond-fast protection has to be designed in from the start rather than added after the fact.