esd protection
**ESD (Electrostatic Discharge) Protection** is the **on-chip circuit design discipline that protects integrated circuits from damage caused by sudden high-voltage discharge events during handling, manufacturing, and operation** — requiring carefully designed clamp circuits and guard structures at every I/O pad and power pin that can safely shunt thousands of volts and amperes in nanoseconds without degrading normal circuit performance, making ESD protection a critical reliability requirement for every chip that ships.
**ESD Events**
| Model | Source | Peak Voltage | Peak Current | Rise Time |
|-------|--------|-------------|-------------|----------|
| HBM (Human Body Model) | Human touch | 2-8 kV | 1-5 A | ~10 ns |
| CDM (Charged Device Model) | Chip itself charged | 250-1000 V | 5-15 A | < 1 ns |
| MM (Machine Model) | Equipment discharge | 100-400 V | 3-5 A | ~15 ns |
| System-level IEC | In-system zap | 2-15 kV | 10-30 A | < 1 ns |
**ESD Damage Mechanisms**
- **Gate oxide rupture**: Even 5-10V across thin oxide (1-2 nm at advanced nodes) → permanent breakdown.
- **Junction burnout**: Excessive current through PN junctions → thermal runaway → melt.
- **Metal fusing**: Current density exceeds electromigration limit → wires melt.
- **Latent damage**: Partial oxide damage → degraded reliability, field failures months later.
**Primary ESD Protection Devices**
- **Grounded-Gate NMOS (ggNMOS)**: NMOS with gate tied to ground → parasitic NPN snapback.
- Trigger voltage: ~7-10V (snapback). Holding voltage: ~4-5V.
- Low area, standard process → most common I/O clamp.
- **Diode strings**: Forward-biased diodes to VDD/VSS → clamp voltage to one diode drop above/below rail.
- Fast turn-on (< 1 ns) → excellent for CDM.
- **SCR (Silicon Controlled Rectifier)**: PNPN latch-up structure intentionally triggered.
- Very high current capacity per area. Risk: Must not trigger during normal operation (latch-up).
- **RC-triggered power clamp**: NMOS clamp between VDD-VSS, triggered by RC time constant detecting fast ESD transient.
- Protects core circuits from power pin ESD events.
**ESD Protection Network Architecture**
```
VDD Rail
|
[Power Clamp]
|
PAD ---[Diode]--- VDD
| |
[Primary [Core
Clamp] Circuit]
| |
PAD ---[Diode]--- VSS
|
[Power Clamp]
|
VSS Rail
```
- **Dual-diode + power clamp**: Most robust for advanced CMOS.
- Positive ESD to pad: Diode to VDD → power clamp → VSS → return.
- Negative ESD to pad: Diode to VSS → direct path.
**Advanced Node ESD Challenges**
| Challenge | Cause | Impact |
|-----------|-------|--------|
| Thinner oxides | Scaling | Lower breakdown voltage → tighter ESD windows |
| FinFET devices | 3D structure | Different snapback behavior, lower ESD robustness per fin |
| High-speed I/O | SerDes > 50 Gbps | ESD cap (50-200 fF) limits bandwidth |
| Multi-domain | Multiple power rails | Cross-domain ESD paths needed |
**ESD Design Rules**
- Every I/O pad must have primary ESD clamp within specified distance.
- Power clamp distributed every 50-200 µm along power rails.
- ESD current path must have sufficient metal width (no bottlenecks).
- Guard rings around ESD devices to prevent latch-up triggering.
ESD protection is **a non-negotiable reliability requirement for every integrated circuit** — a chip without adequate ESD protection will suffer yield loss in manufacturing from handling damage and field failures from user interaction, making ESD design one of the few areas where a single engineering oversight can render an otherwise perfect chip commercially unshippable.