esd

**ESD Protection Design** is the **design of circuits to survive electrostatic discharge — handling human body model (HBM), charged device model (CDM), machine model events — using gg-NMOS clamps, diode networks, and power clamps to safely discharge charge without damaging gate oxide — essential for yield and reliability**. ESD protection is invisible but critical. **Human Body Model (HBM) and Charged Device Model (CDM)** ESD failure modes: (1) HBM (human body model) — person charged to high voltage (kV), touches product, discharges through chip (slow discharge, ~100 ns, high current ~A), (2) CDM (charged device model) — chip itself charged (during handling, packaging), then discharges through pins to ground or between pins (fast discharge, ~1 ns, very high current, >10 A). HBM is slower and easier to protect against; CDM is faster and more challenging (requires faster ESD devices). Both must be designed for: typical spec is HBM >2 kV, CDM >500 V. **ESD Design Window** ESD clamp must: (1) trigger (turn on) above Vdd+10% (above normal operating voltage), (2) clamp voltage below substrate breakdown (Vbdii, typically 6-8 V for 28 nm, higher for older nodes), (3) not interfere with normal operation (no leakage, no capacitive loading). Design window: trigger voltage < Vclamp < Vbdii. Example: Vdd=1.0 V, trigger=1.1 V, Vbdii=7 V, design window 1.1-7 V. Wider window provides margin (easier design); narrower window is challenging (tight control). At advanced nodes with lower Vdd and lower Vbdii, design window shrinks (5-10 V window at 7 nm vs 10+ V at 28 nm). **Gg-NMOS (Gate-Grounded NMOS) as Primary Clamp** Gate-grounded NMOS is the workhorse ESD device: n-MOSFET with gate connected to ground (tied low). During ESD (high pin voltage), drain-to-source junction is reverse-biased (drain positive, source at ground). At high voltage (punch-through region), device conducts heavily (secondary breakdown current conduction mode). Advantages: (1) turns on at predictable voltage (punch-through ~6-8 V), (2) high current carrying (W/L optimized for high current, ~A), (3) low leakage (gate tied low, no channel, only junction leakage), (4) compact (single transistor). Current flows from pin to ground, discharging ESD charge safely. **Diode-Based ESD Network** ESD networks for differential I/O (e.g., USB, LVDS) often use back-to-back diodes (clamp from D+ to D- and from each to ground via diodes). Advantages: (1) no interfering DC current (diodes block current at nominal Vdd), (2) fast triggering (diode forward voltage ~0.7 V, triggering quickly), (3) small area. Disadvantages: (1) leakage from reverse-biased diodes (higher than gg-NMOS), (2) temperature sensitivity (diode voltage-temperature coefficient ~2 mV/K). Diode-based networks are preferred for differential signals; gg-NMOS for single-ended supplies. **ESD Power Clamp (RC-Triggered)** Power clamp is an ESD device on the power rail (between Vdd and ground), turning on during ESD to discharge Vdd. RC-triggered power clamp uses RC network to detect rapid dI/dt (ESD signature): (1) current spike into logic from ESD, (2) creates voltage transient on power supply (via parasitic inductance), (3) RC network detects dV/dt, (4) triggers transistor gate to turn on power clamp, (5) clamp conducts, discharges charge. Power clamp prevents Vdd voltage from rising above safe limit (which would damage all logic). Power clamp trigger voltage is set via RC network: lower capacitance = faster trigger, higher capacitance = slower trigger. **ESD Co-Design with I/O Circuit** ESD protection adds capacitive loading (~0.5-5 pF per I/O) and parasitic inductance (~nH), affecting I/O circuit timing and signal integrity. I/O circuit design must account for: (1) ESD capacitance as load (reduces speed slightly), (2) ESD parasitic inductance (can cause ringing on fast transitions). Co-design: (1) I/O driver upsized slightly to overcome ESD capacitance, (2) ESD device placed close to I/O (minimize inductance), (3) ESD device sized (W/L) to achieve target voltage clamp without excessive loading. I/O timing spec often includes ESD-induced delay (~5-10% margin for ESD loading). **CDM Challenge at Advanced Nodes** Charged device model (CDM) is increasingly challenging at advanced nodes: (1) lower Vdd (0.7-0.9 V at 7 nm) reduces design window (trigger must be