electrostatic discharge protection

**Electrostatic Discharge (ESD) Protection Design** is the **on-chip circuit strategy that protects the ultra-thin gate oxides and narrow junctions of advanced CMOS transistors from destruction by electrostatic discharge events — where a human body discharge (2-4 kV, ~1 A peak for ~100 ns) or charged device discharge (500-1000V, ~10 A peak for ~1 ns) would instantly rupture the 1.5-3nm gate oxide without robust ESD clamp circuits at every I/O pad and between all power domains**. **ESD Threat Models** - **HBM (Human Body Model)**: Simulates a person touching a chip pin. 100 pF capacitor discharged through 1500 Ω resistor. Peak current ~1.3 A at 2 kV. Duration ~150 ns. Industry standard: survive 500V-2000V HBM. - **CDM (Charged Device Model)**: The chip itself becomes charged during handling, then discharges rapidly through a pin that contacts a grounded surface. Very fast (<2 ns), very high peak current (5-15 A). Often the most challenging ESD specification — requires low-inductance discharge paths. - **MM (Machine Model)**: Simulates contact with charged manufacturing equipment. 200 pF, 0 Ω — essentially a capacitor dump. Less commonly specified today. **ESD Protection Circuit Elements** - **Primary Clamp (I/O Pad)**: Large diodes or grounded-gate NMOS (GGNMOS) connected from each I/O pad to VDD and VSS. The clamp must turn on rapidly (<1 ns) when the pad voltage exceeds the trigger voltage (5-8V) and sink the full ESD current (1-10 A) without the pad voltage exceeding the oxide breakdown voltage. - **Secondary Clamp**: Smaller devices closer to the protected circuit that limit the voltage reaching the core transistors. Add series resistance to slow the ESD pulse. - **Power Clamp**: Large NMOS between VDD and VSS that turns on during an ESD event (detected by an RC timer network) to provide a low-impedance discharge path between power rails. Essential for CDM protection — without it, charge stored on VDD has no path to VSS. **Whole-Chip ESD Network** - **ESD Bus**: A dedicated low-resistance metal bus connecting all I/O pad clamps to the power clamps. The bus resistance directly adds to the ESD discharge path — must be <1 Ω for CDM compliance. - **Cross-Domain Clamps**: When multiple power domains exist, ESD clamps between domains (VDD1↔VDD2, VSS1↔VSS2) ensure that discharge current can flow between any two pins regardless of domain. - **ESD Simulation**: SPICE simulation with ESD device models (validated to TLP — Transmission Line Pulse measurements) verify that the protection network keeps all node voltages below safe limits during HBM and CDM events. **Design Trade-offs** Larger ESD clamps provide more protection but add parasitic capacitance (0.2-2 pF per pad) that degrades high-speed signal integrity. For multi-gigabit SerDes pads, low-capacitance clamp topologies (small diodes + series resistance + active clamp) are essential. The ESD-performance trade-off is one of the most critical I/O design decisions. ESD Protection is **the survival infrastructure that every chip must have** — invisible during normal operation but absolutely critical during the handling, assembly, and testing phases where a single unprotected path to a gate oxide means instant destruction of a chip that took months to design and millions to develop.