chip packaging

**Chip Packaging** — encapsulating a semiconductor die and connecting it to the outside world, providing mechanical protection, electrical connections, and thermal management. **Package Types** - **Wire Bond**: Gold/copper wires connect die pads to package leads. Mature, low cost. Used for low pin-count devices - **Flip Chip**: Die flipped upside down, solder bumps connect directly to substrate. Shorter connections, better performance. Standard for CPUs/GPUs - **BGA (Ball Grid Array)**: Solder balls on package bottom. High pin count, good for PCB mounting - **QFN/QFP**: Leaded packages for cost-sensitive applications **Advanced Packaging** - **2.5D (Interposer)**: Multiple dies on a silicon interposer with through-silicon vias. AMD EPYC, NVIDIA H100 - **3D Stacking**: Dies stacked vertically with TSVs (Through-Silicon Vias). HBM memory - **Chiplets**: Disaggregated design — multiple small dies in one package instead of one large die. AMD Zen, Intel Ponte Vecchio - **Fan-Out Wafer Level (FOWLP)**: Redistribution layer packaging at wafer level. Apple processors - **Hybrid Bonding**: Direct copper-to-copper bonding at sub-micron pitch. Next-gen 3D integration **Packaging** is now as critical as transistor scaling for performance — "More than Moore" advances come from advanced packaging.