chiplet integration design

**Chiplet-Based Design and Integration** is the **modular chip architecture that decomposes a monolithic SoC into multiple smaller dies (chiplets) — each optimized independently for function, process node, and yield — interconnected through advanced packaging (2.5D interposer, 3D stacking, or organic substrate) using high-bandwidth die-to-die interfaces, enabling larger effective chip sizes, heterogeneous technology mixing, and dramatic improvements in design reuse and manufacturing yield**. **Why Chiplets** Monolithic die yield drops exponentially with die area: a 600mm² die on a process with 0.1 defects/cm² has only ~55% yield. Splitting into four 150mm² chiplets raises yield to ~86% per chiplet (~55% composite, but each chiplet is independently testable — good chiplets replace bad ones). Additionally, different chiplets can use different optimal process nodes: 3nm for compute, 5nm for I/O, 7nm for analog. **Die-to-Die Interconnect Standards** - **UCIe (Universal Chiplet Interconnect Express)**: Industry standard (Intel, AMD, ARM, TSMC, Samsung) for die-to-die communication. Defines physical layer (bumps, signaling), protocol layer (PCIe, CXL), and management. Standard bump pitch: 25 μm (standard package) or 36 μm for organic substrate. - **Bandwidth**: UCIe advanced package achieves 28.125 GB/s per mm of edge (1317 Gbps per mm at 32 GT/s). A 10mm edge delivers 280+ GB/s — sufficient for cache-coherent interconnect between compute chiplets. - **BoW (Bunch of Wires)**: Simpler, lower-latency die-to-die protocol for known-good-die connections within a package. **Packaging Technologies for Chiplets** - **2.5D (Interposer)**: Chiplets mounted on a silicon or organic interposer with fine-pitch wiring (0.4-2 μm line/space). TSMC CoWoS, Intel EMIB. Provides high density die-to-die connections through the interposer redistribution layers. - **3D Stacking**: Chiplets stacked vertically with through-silicon vias (TSVs). Highest bandwidth density (>1 TB/s between stacked dies) but thermal challenges from stacked power dissipation. - **Organic Substrate (Fan-Out)**: Chiplets embedded in a molded fan-out wafer with redistribution layers. Lower cost than silicon interposer but coarser interconnect pitch (2-10 μm). **Design Challenges** - **Partitioning**: Deciding which functions go on which chiplet to minimize die-to-die traffic while respecting die area and yield constraints. Data-intensive interfaces (memory controller ↔ cache) should not cross chiplet boundaries if possible. - **Coherence Across Chiplets**: Maintaining cache coherence across chiplet boundaries adds latency (5-20 ns per hop) compared to monolithic (~1-2 ns). Coherent protocols (CXL.cache, AMD Infinity Fabric) minimize but cannot eliminate this overhead. - **Power Delivery**: Each chiplet needs dedicated power delivery. Package-level power distribution becomes as complex as chip-level. - **Testing**: Each chiplet is tested independently (Known Good Die — KGD) before assembly. Defective chiplets are discarded, saving the cost of the package and other good chiplets. Chiplet Architecture is **the semiconductor industry's answer to Moore's Law economics** — maintaining performance and transistor count scaling by assembling optimized pieces rather than building ever-larger monolithic dies, fundamentally changing how chips are designed, manufactured, and integrated.