chiplet packaging cowos foveros

**Chiplet-Based SoC Design: Modular Integration via UCIe Standard — disaggregated system-on-chip with independent dies connected via standard chiplet interface enabling mixed-process node and rapid IP reuse** **Chiplet Disaggregation Benefits** - **Yield Advantage**: smaller dies (chiplets) have higher yield than monolithic (yield scales as die_area^(-α) where α~2-3), cost per chiplet lower - **Mixed-Node Fabrication**: CPU on 5nm, GPU on 7nm, memory on mature node, optimizes cost/performance per block - **IP Reuse**: chiplet platform enables third-party IP integration (analog, RF, I/O) without full-chip redesign - **Design Flexibility**: swap chiplets (upgrade CPU, add accelerators) without redesigning entire SoC, modular architecture **UCIe Standard (Universal Chiplet Interconnect Express)** - **Physical Layer**: parallel wire interface (8-64 lanes) or serial PHY (Gbps channels), sub-µm pitch capability - **Protocol**: credit-based packet routing, coherence support (snooping for shared memory), low-latency transactions - **Multiple Tiers**: tier-1 (fine-grain, high-bandwidth interconnect within package), tier-2 (multi-chip module), tier-3 (board-level interconnect) - **Ecosystem Support**: TSMC, Intel, Samsung, AMD, ARM backed standard, enabling broad chiplet ecosystem **Die-to-Die (D2D) Physical Layer** - **Parallel Interface**: multiple parallel wires (8-64 lanes) for higher bandwidth, simpler signaling, but requires careful layout/matching - **Serial PHY**: high-speed differential pairs (8-16 GHz per lane), lower pin count vs parallel, signal integrity critical (equalization, CDR) - **Interposer-Based**: chiplets bonded to silicon interposer (passive silicon carrier), TSV via interposer for fine-pitch interconnect - **Direct Bonding**: face-to-face chiplet connection (no interposer), enables tighter integration, higher density **Chiplet Interface Characteristics** - **Bandwidth**: parallel interface (128-lane × 20 Gbps = 320 GB/s), serial (8 lanes × 16 Gbps = 16 GB/s per lane) - **Latency**: chiplet-to-chiplet latency ~10-20 ns (vs ~3 ns intra-die), adds overhead for cross-chiplet traffic - **Power**: interconnect power budget (~10% of total), short traces reduce I²R losses vs external I/O **Packaging Technologies** - **CoWoS (Chip-on-Wafer-on-Substrate)**: chiplets placed on interposer, then assembled on substrate (Intel Arc GPU, Apple M-series), mature but expensive - **Foveros (Intel)**: face-to-face die stacking (logic die on top, memory die below), direct bonding for tight coupling, used in Alder Lake (P+E core chiplets) - **EMIB (Embedded Multi-die Interconnect Bridge)**: chiplets flanking thin silicon bridge (with interconnect), 55 µm pitch bridges (Intel Stratix 10 NX) - **Advanced Packaging**: UCIe roadmap includes UCIe-HPC (coherent, lower latency) for hyperscale CPUs **Heterogeneous Chiplet Integration** - **Partitioning Strategy**: determine which functions partition into chiplets (memory separation obvious, CPU vs GPU less clear) - **Interface Definition**: specify which signals cross chiplet boundary, design chiplet interface controller (protocol translation, buffer management) - **Synchronization**: chiplets may have different clock domains, async interface or phase-locked via synchronizer - **Power Distribution**: each chiplet has local voltage regulators, coordinated power gating across chiplets **Test Methodology** - **Pre-Bond Testing (KGD)**: known-good die (KGD) screening before assembly, on-die test circuitry (BIST, scan) - **Post-Bond Testing**: test chiplet connectivity post-bonding (parameter testing at speed), detect opens/shorts in D2D interface - **Yield Learning**: test data collected to improve subsequent yields (correlation analysis, fault signature analysis) **Ecosystem and Strategies** - **TSMC Chiplet Alliance**: open platform, chiplet IP exchange, design templates - **Intel Foveros Ecosystem**: interconnect standard, partner chiplet integration - **AMD**: Ryzen/EPYC MCM (multi-chip module) with HyperTransport interconnect, mature chiplet methodology **Design Challenges** - **Latency Budget**: cross-chiplet traffic adds delay, critical for real-time control or performance-sensitive paths - **Verification Complexity**: simulating chiplet interactions, formal verification of protocol, corner cases in handshake - **Manufacturing**: chiplet alignment, bonding yield, warpage post-assembly **Future**: chiplet design expected standard by 2025-2030, UCIe standardization enables open ecosystem (vs proprietary interconnects), heterogeneous integration dominant for cost-optimization.