clock domain crossing

**Clock Domain Crossing (CDC)** — the challenge of safely transferring signals between logic driven by different clocks, where metastability can cause unpredictable failures. **The Problem** - When a signal crosses from clock domain A to clock domain B, it may change exactly when domain B's clock samples it - Result: Metastability — the flip-flop enters an unstable state between 0 and 1 - Metastable output can propagate incorrect values downstream **Solutions** - **2-Flip-Flop Synchronizer**: Signal passes through two back-to-back flip-flops in the receiving domain. First FF may go metastable, but resolves before second FF samples it. For single-bit signals - **Gray Code Counter**: For multi-bit bus crossing — only one bit changes at a time. Used for FIFO pointers - **Async FIFO**: Dual-clock FIFO with Gray-coded pointers crossing domains. Standard for data buses - **Handshake Protocol**: REQ/ACK signaling between domains for control signals - **MUX Synchronizer**: For multi-bit data with a valid/enable signal **CDC Verification** - Static CDC analysis tools identify all domain crossings - Flag missing synchronizers, multi-bit crossings, reconvergence issues - Tools: Synopsys SpyGlass CDC, Cadence Conformal **CDC bugs** are among the hardest to detect in simulation — they depend on exact clock phase relationships and can be intermittent.