clock tree synthesis

**Clock Tree Synthesis (CTS)** is the **process of distributing the clock signal from the source to all sequential elements with balanced delay and minimum skew** — ensuring all flip-flops receive the clock edge at nearly the same time for correct circuit operation. **Why CTS Matters** - Clock period = max combinational path delay + setup time + skew + jitter. - Skew directly steals from the timing budget: 100ps skew on a 1GHz design wastes 10% of the clock period. - Bad skew: Flip-flop A sees clock 300ps before Flip-flop B → path between A and B must complete in 700ps instead of 1000ps. **CTS Goals** - **Insertion Delay**: Total delay from clock source to all leaf flip-flops (minimize or target). - **Skew**: Difference in arrival time between earliest and latest flip-flop clock. Target: < 5–10% of clock period. - **Transition Time**: Slew at each clock node. Poor slew → increased uncertainty and power. - **Power**: Clock network is 20–40% of chip dynamic power — minimize buffer count and wire length. **CTS Algorithm** 1. **Clock Tree Topology Selection**: H-tree, X-tree, balanced binary tree. 2. **Buffer Insertion**: Iteratively insert clock buffers to drive the fanout and balance delay. 3. **Sizing**: Size each buffer to achieve target slew at its output. 4. **Shielding**: Add ground/power shields around critical clock wires to reduce noise coupling. 5. **Skew Balancing**: Adjust buffer placements or insert delay cells to equalize arrival times. **Useful Skew (Skew Scheduling)** - Deliberately unbalance clock to help timing: - Send clock to receiving FF earlier → more time for data path. - Standard CTS targets zero-skew; useful CTS targets minimum period. **Multi-Clock Domains** - Each clock domain synthesized independently. - Clock domain crossing (CDC) paths must use synchronizers, not CTS balancing. **Tools** - Cadence Innovus, Synopsys IC Compiler II — built-in CTS. - Synopsys CTS Compiler — standalone. - Sign-off: Check skew and transition at all PVT corners. Clock tree synthesis is **one of the most impactful physical design steps** — a well-designed clock tree enables aggressive performance targets while poorly-designed trees with large skew and poor transition times can make a chip fail even if all combinational timing paths meet.