CMOS 1963 Two Opposing Transistors Solve Power Problem

# Why Two Opposing Transistors Solve the Power Problem 1962 Closed On: Zero Current, Not Just Zero Gate Current

## 1. Why a Near-Zero Gate Current Was Never the Whole Answer

This step pairs a PMOS transistor and an NMOS transistor with their gates tied together as a single input and their drains tied together as a single output, source of the PMOS device to the supply and source of the NMOS device to ground, and shows that in either static logic state exactly one of the pair conducts while the other sits in cutoff — meaning no continuous current path exists from supply to ground at all, a genuinely stronger claim than 1962's own closing figure of merit made. That earlier figure of merit put a single transistor's gate current, essentially zero, in its denominator to argue for high gate density under a fixed power budget — but a complete logic gate built from a single-channel MOS transistor still needs some kind of load, a resistor or an always-on second transistor, to pull its output to the opposite rail when the switching device is off, and that load draws continuous current throughout every cycle the gate spends in its active state. This step's complementary pair eliminates that load's static current too, by using an active device as the load that switches off precisely when the other device switches on.

$$I_{\text{supply}} = \frac{V_{DD}}{R_{\text{ON}} + R_{\text{OFF}}} \approx \frac{V_{DD}}{R_{\text{OFF}}} \to 0$$

where $R_{\text{ON}}$ is the channel resistance of whichever transistor in the pair is currently conducting, $R_{\text{OFF}}$ the enormous channel resistance of whichever transistor is currently in cutoff, and $I_{\text{supply}}$ the current actually drawn from the supply through the series path formed by both channels — because the two resistances sit in series and $R_{\text{OFF}}$ dwarfs $R_{\text{ON}}$ by many orders of magnitude, the sum is dominated entirely by whichever transistor happens to be off, driving the static supply current toward zero regardless of which half of the pair that happens to be.

Whichever Device Is Off Dominates the Series Sum both static input states, side by side INPUT LOW PMOS, RON, conducting NMOS, ROFF, cutoff series sum dominated by ROFF INPUT HIGH PMOS, ROFF, cutoff NMOS, RON, conducting series sum dominated by ROFF again Isupply = VDD / (RON + ROFF) ≈ VDD / ROFF one device is always off — the pair never offers a low-resistance path through both at once

## 2. Real Diagram: The Complementary Pair, Drawn as the Circuit It Actually Is

The schematic below is this series' first circuit diagram rather than a cross-section, because what makes this structure work is a topological fact — gates tied together, drains tied together, sources split between the supply and ground — not yet a specific physical fabrication this step has built.

The Complementary Inverter, as a Circuit gates tied together, drains tied together, sources split between the two rails VDD PMOS output NMOS ground input, both gates tied together the topology alone, independent of fabrication, is what forces exactly one device to conduct at a time

## 3. The Load This Project's Own 1962 Series Still Needed, Now Eliminated

Every logic gate the 1962 series' own closing argument implicitly assumed was built from a single switching transistor and some kind of passive or always-on load — a resistor, or a second transistor biased permanently into weak conduction — needed to pull the output to the opposite rail whenever the switching transistor turned off. That load drew current continuously whenever the gate sat in the state requiring it, which is exactly the limitation 1962's own closing figure of merit left unaddressed, because that figure of merit characterized a single transistor's own gate current, not a complete gate's supply current. This step's complementary pair replaces that passive load with an active device of the opposite type, wired so it turns off precisely when the switching device turns on — the same structural logic 1962's own Step 9 showed this device family offers at the transistor level, now applied at the circuit level for the first time in this project's history.

Step 1 does not merely repeat 1962's own claim about near-zero gate current; it shows that pairing two opposing transistors eliminates the one source of continuous current 1962's single-transistor argument could never fully close.

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