CMOS 1963 Wire Pair First Two Transistor Logic Gate

# Wire the Pair Into This Project's First Two-Transistor Logic Gate: The Resistor 1960 Had to Size, This Gate Doesn't Need at All

## 1. Why This Gate Needs No Component This Project Has Ever Had to Size Before

This step deposits and patterns metal interconnect, using the identical metallization technique the 1962 series' own Step 4 established, to tie the two transistors Step 4 just finished into a working logic gate — PMOS and NMOS drains joined as a single output, both gates joined as a single input, the PMOS source tied to the supply rail and the NMOS source tied to ground — producing this project's first complete logic gate built from exactly two transistors and no resistor at all. The 1960 Micrologic series built its own logic gates around a diffused resistor, sized to balance two requirements that were always in tension: small enough to switch quickly, large enough to limit the steady current it drew whenever the gate held the state that pulled current through it. That resistor could be optimized, but it could never be escaped, because a single switching transistor always needed something passive to pull its output to the opposite rail. This step's wiring removes that component from the circuit entirely, replacing a passive load with the second transistor's own active behavior — the circuit-level realization of exactly what Step 1 described before any of it had been physically built.

$$P_{\text{resistor-loaded}} = \frac{V_{DD}^2}{R_{\text{load}}}$$

where $P_{\text{resistor-loaded}}$ is the steady power a 1960-style resistor-loaded gate dissipates whenever its switching transistor holds the state that pulls current through the load resistor $R_{\text{load}}$ — a quantity every earlier logic gate this project has built had to accept and optimize, and a quantity this step's wiring makes irrelevant, because the circuit this step produces contains no resistor anywhere in it for that power to be dissipated across.

A Resistor Sized, Versus a Resistor That Isn't There 1960's own loaded gate, beside this step's complementary gate 1960 — RESISTOR-LOADED GATE Rload switching transistor P = VDD² / Rload whenever the state pulls current 1963 — COMPLEMENTARY GATE PMOS, active load NMOS, switching no resistor anywhere — nothing to dissipate P across Presistor-loaded = VDD² / Rload — a quantity this gate has nothing left to apply it to the active load does not replace the resistor's job with a better resistor; it removes the resistor's job

## 2. Real Diagram: The First Complete Gate Layout, Four Connections, No Fifth Component

The layout below shows the actual metal wiring this step produces — four connections joining the two transistors into a single gate, with no resistor anywhere in the layout for a fifth connection to even reach.

Four Metal Connections, One Finished Gate input, output, VDD rail, ground rail — nothing else to wire PMOS NMOS VDD rail output, drains tied ground rail input, gates tied every connection here is load-bearing — none of them exist to feed a resistor

## 3. The Trade-Off 1960 Had to Optimize, This Gate Has Nothing Left to Optimize

The 1960 Micrologic series' own Step 1 and Step 4 established how to diffuse a resistor and size its value, and every logic gate that series built afterward lived inside the tension that sizing created: a smaller resistor switched faster but dissipated more steady power, a larger resistor dissipated less power but switched slower, and no value of that resistor escaped the trade-off entirely — the resistor could be tuned, never eliminated. This step's wiring does not tune that trade-off to a better point; it removes the component the trade-off was ever about. The active PMOS load this step connects into the circuit behaves, from the output node's perspective, like a load that is either very low resistance or very high resistance depending entirely on which logic state the gate holds, which is exactly the behavior a single fixed resistor could never provide at any value.

Step 5 does not optimize the resistor every earlier logic gate in this project had to carry; it wires a circuit that has no resistor in it to optimize at all, closing the loop this series opened in Step 1 with an actual, physically finished gate rather than a claim about one.

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