CMOS 1963 Diffuse Well to the Depth Devices Need
# Diffuse the Well to the Depth Devices Actually Need: The Same Lateral-Spread Fact, a Much Bigger Number This Time
## 1. Why a Deep Diffusion Costs Far More Chip Area Than a Shallow One Ever Did
This step runs the furnace drive-in that actually gives Step 2's well the depth it needs, using the identical diffusion time-temperature relation this project has relied on since 1954 — but because a well must reach several times deeper than any source or drain diffusion this project has built before, the same lateral-spread fact 1959 first established for junction coverage now costs this series a genuinely larger amount of chip area than it ever cost a shallow diffusion. Every diffusion this project has driven since 1954 spreads sideways under its own mask edge by a roughly fixed fraction of however deep it goes vertically — a ratio this project measured once, in 1959, and has reused ever since. That ratio has not changed. What has changed is the target depth itself: a well diffused several microns deep spreads sideways by several microns too, a lateral encroachment many times larger in absolute terms than the fraction-of-a-micron spread a shallow source or drain diffusion was ever responsible for, and that encroachment eats directly into the spacing this series must leave between the well and the neighboring NMOS device it was never meant to touch.
where $x_{j,\text{well}}$ is the well's own vertical depth after a drive-in of time $t$ at diffusion coefficient $D$, $A$ a constant set by the dopant's own solubility and the furnace conditions, and $x_{\text{lateral}}$ the sideways spread beneath the mask edge — the same 0.8 ratio this project first measured in 1959 for junction coverage and reused in 1962 for channel length, applied here to a target depth large enough that the resulting lateral number is no longer a minor correction but a real chip-area cost this series must plan around from the start.
## 2. Real Diagram: A Mask Boundary, and Where the Well Actually Ends Up
The top-down layout below shows the well exactly as a mask designer has to plan for it — not where the mask edge was drawn, but where the well's own lateral spread actually puts its boundary, and the minimum keep-out spacing this series must leave before the neighboring NMOS device can safely begin.
## 3. The Same Ratio, Reused a Third Time, at a Scale That Finally Matters for Layout
This project measured the lateral-to-vertical diffusion ratio exactly once, in 1959, to manage how far a base or emitter diffusion crept sideways under an oxide edge, where the absolute distances involved were small enough that the resulting margin was a precision concern rather than a space-planning one. The 1962 MOSFET series reused the identical ratio to show how a diffused source and drain narrow a mask-drawn channel gap into a shorter effective channel length, again at a scale measured in fractions of a micron. This step reuses the same ratio a third time, but at a depth several times larger than either earlier context ever required, which changes what kind of problem the lateral spread actually is: no longer a correction to a measurement, but a real amount of chip area that a layout must reserve before two adjacent structures can be placed safely near each other. The physics has not changed at all since 1959; only the scale at which this project has now had to apply it has.
Step 3 does not discover a new fact about how dopants spread sideways while diffusing; it is the first step in this project's history where a fact established for precision turns out to matter for area instead.