CMOS 1963 Measure Switching Power Delay Tradeoff

# Measure Switching Power and the Power-Delay Trade-Off: The Power Step 6 Never Claimed to Eliminate

## 1. Why Near-Zero Static Power Was Never the Whole Picture

This step measures the power this gate actually dissipates while switching — charging and discharging whatever load capacitance sits on its output every time it changes state — because Step 6's near-zero static current measurement said nothing about the power this circuit pays during the brief transition between states, and that transition power is real, measurable, and grows directly with how often the gate switches. Every time the output moves from one rail to the other, current flows through whichever transistor is conducting to charge or discharge the load capacitance sitting on that output — the gate capacitance of whatever this gate drives next, plus this series' own overlap capacitance and wiring capacitance — and that charging current dissipates real energy on every single transition, energy that Step 6's static measurement, held fixed in one state at a time, was never built to see at all.

where $C_L$ is the load capacitance this gate's output must charge and discharge each cycle, $V_{DD}$ the supply voltage, and $f$ the switching frequency — unlike Step 6's static current, which held essentially flat regardless of how often the gate switched, this dynamic power term grows linearly with switching frequency, which means the near-zero static advantage this series has built toward is a genuine advantage at low switching rates, but not an advantage that survives at every frequency a real circuit might need to run at.

## 2. Real Diagram: Current Pulses at Every Edge, Not a Steady Draw

The waveform below shows what this step's measurement actually captures — brief current pulses from the supply at each switching edge, charging and discharging the output load, in direct visual contrast to Step 6's flat, near-zero reading between edges.

## 3. Completing the Picture 1962's Own Step 9 Left Open

The 1962 MOSFET series' own Step 9 measured a direct, honest comparison against the epitaxial bipolar transistor this project had just finished, and the result split cleanly along two axes: slower switching, but near-zero steady gate current. This step completes the equivalent picture for this series, and the completed picture is more nuanced than Step 6 alone suggested. This series' static power advantage, verified in Step 6, is real and does not depend on how fast the gate switches — but this step's dynamic power term does depend on switching frequency, and grows without bound as frequency increases, until it dominates the total power this gate draws regardless of how small its static leakage was ever measured to be. The honest claim this series can make is not that complementary logic eliminates power consumption, but that it eliminates the specific power term — a resistor's steady current, or a single-channel device's static leakage — that scaled with how long a gate held a given state rather than with how often it changed states.

Step 8 does not contradict Step 6's own result; it bounds it, showing exactly the condition — low switching frequency — under which this series' static-power advantage is the whole story, and the condition under which it is not.