CMOS Logic 1980s CMOS Becomes the Default Vlsi Microprocessors and Lasting Dominance

# CMOS Becomes the Default: VLSI, Microprocessors, and a Dominance That Outlasts 1980s Numbers

## 1. Why the Inverter's Own Transfer Curve Is the Reason Density Scaled at All

Every step in this series since Step 1 has used the complementary inverter as its basic unit without yet asking what happens to that inverter's output as its input sweeps continuously between the two rails, and it is exactly that continuous transfer characteristic — not the static endpoints Step 6 measured — that let CMOS absorb the gate counts the VLSI era demanded. A CMOS inverter's output does not snap between rails; it traces a curve that stays pinned near $V_{DD}$ while the input sits below the NMOS threshold, falls steeply through a narrow transition region once both devices conduct simultaneously, and settles near ground once the input clears the PMOS's own threshold from the other side. That steep transition region is the full-rail noise margin every later step in this project's wider lineage depends on without saying so: a CMOS gate's output swings essentially all the way between rails in both logic states, giving the next gate's input the largest possible margin against noise, crosstalk, and the manufacturing variation that only grows as feature size shrinks toward the limits this project's own scaling series have chased since 1954.

$$V_{OH} \approx V_{DD}, \qquad V_{OL} \approx 0, \qquad \left|\frac{dV_{out}}{dV_{in}}\right|_{\text{transition}} \gg 1$$

where $V_{OH}$ and $V_{OL}$ are the inverter's high and low output levels, each pinned within millivolts of a rail because the opposite-type transistor is driven fully off rather than merely biased into a weaker conduction state, and the transition-region slope is large because both devices conduct together only across a narrow span of input voltage — a ratioed NMOS inverter, by contrast, never reaches a true $V_{OL}$ near zero at all, because its always-on load device keeps pulling current even in the logic-low state, the same structural limitation Step 11 already traced back to NMOS's static power term.

The Transfer Curve That Full-Rail Noise Margin Comes From V_out against V_in, CMOS against a ratioed NMOS inverter for contrast V_in, 0 to V_DD V_out CMOS: pinned near both rails, steep transition ratioed NMOS: V_OL never reaches ground V_OH ≈ V_DD, V_OL ≈ 0, |dV_out/dV_in| ≫ 1 across the transition this margin is what lets millions of gates stay correctly switched on one die

## 2. Real Diagram: Why NAND and NOR Win the Transistor-Count Argument VLSI Needed Won

A two-input CMOS NAND or NOR gate needs exactly four transistors — two series or parallel NMOS devices and the complementary PMOS pair — the same four-transistor discipline Step 5 established for a single inverter's pair, extended by one series-parallel branch rather than by a wholly new structure, which is exactly the property that let gate-count-per-die keep climbing through the VLSI era.

Four Transistors, Two Gate Types, One Recurring Pattern PMOS devices in parallel mirror NMOS devices in series, and vice versa, for every added input 2-INPUT NAND 2 PMOS, in parallel 2 NMOS, in series 2-INPUT NOR 2 PMOS, in series 2 NMOS, in parallel transistor count grows linearly with fan-in, the same discipline that made millions of gates per die practical

## 3. ESD Protection, VLSI Density, and a Dominance the 1980s Numbers Only Started

A CMOS gate's input is the gate of a MOS transistor directly, separated from the channel by an oxide thin enough that the device can be switched on by a few volts — exactly the structure that makes it vulnerable to the static discharge an assembler's own hand can deliver, a failure mode no bipolar TTL or ECL input ever had to defend against in the same way, because a bipolar base draws real current rather than presenting a bare capacitor to the outside world. Every CMOS part built since the 74HC/74HCT family Step 19 introduced carries a small clamping structure at each input pin specifically to shunt that discharge safely to the supply rails before it can punch through the gate oxide underneath — a cost as unavoidable for CMOS as the guard ring Step 13 priced out for latchup, and one more line item in the same honest accounting Step 16 performed for power.

None of those added costs — guard rings, decoupling capacitance, input ESD clamps — ever came close to threatening the structural advantage Steps 1 through 11 built and proved: a logic family whose static power term is zero by topology, not by process tuning, scales to far higher gate counts under a fixed power budget than any family that must dissipate current continuously just to hold a state. That scaling is exactly what the VLSI era needed and exactly what let the microprocessor generations following this series' own 1980s snapshot put far more logic on a single die than the ratioed NMOS lineage traced through Step 11's own HMOS comparison could ever have supported at the same power budget. CMOS did not win the 1980s because its numbers were better at any one moment this series measured; it won because every other logic family this project has documented — the bipolar line since 1947, the NMOS lineage through HMOS, even first-generation 4000-series CMOS itself — eventually ran into a cost or a ceiling that complementary logic's own topology never had to pay.

Step 20 does not claim CMOS wins every comparison a later series might run against it; it closes this series by naming the one property that makes CMOS's dominance durable rather than momentary — a static power term that is structurally absent rather than merely small — and hands that property forward as the default assumption any later series documenting digital logic at meaningful scale should now begin from, the same way Step 10 once proposed and Steps 11 through 19 have since confirmed in practice.

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