CMOS Crossover 1980 Twin Well Latchup Density Penalty

# Build Two Wells on One Substrate, and Confront the Parasitic Transistor Density Reintroduces

## 1. State What Housing Both Device Types on One Substrate Actually Requires

A complementary pair needs an NMOS transistor and a PMOS transistor coexisting on a single piece of silicon, and the two devices need opposite-polarity local substrate material: NMOS needs a p-type region to sit in, PMOS needs an n-type region. Early CMOS, including the 1962–1963 series' original devices, solved this with a single well — typically an n-well diffused into a p-type substrate, hosting the PMOS device while the NMOS device used the substrate directly. That approach was sufficient at the device counts and spacings 1963 worked with.

Twin-well CMOS, the structure this crossover-era series documents, instead builds two independently engineered wells — an n-well for PMOS and a p-well for NMOS — both diffused into a more lightly doped starting substrate. The reason is direct: single-well CMOS ties one device's body doping to whatever the starting wafer happened to be, which constrains how aggressively either device's threshold and punch-through behavior can be tuned independently. Twin wells, like Step 2 of the HMOS series used ion implantation to decouple the load device from the switching transistor, decouple the NMOS well's doping profile from the PMOS well's doping profile, so each device type can be optimized on its own terms as both shrink toward 1980s densities.

Twin Wells Decouple Both Devices From a Shared Substrate single-well CMOS (1963) versus twin-well CMOS (1980) on the same die cross-section SINGLE-WELL CMOS (1963) n-well: PMOS substrate: NMOS NMOS body doping fixed by starting wafer only PMOS well is independently tunable sufficient at 1963's device spacing TWIN-WELL CMOS (1980) n-well: PMOS p-well: NMOS both device bodies independently implanted lightly doped starting substrate underneath each device tuned on its own terms TWO WELLS TOUCHING ON ONE SUBSTRATE the n-well/p-well junction and the layered doping beneath it forms a structure that was not present in single-well CMOS — Section 2 that structure is a parasitic bipolar device latchup — the cost of the independence twin wells bought

## 2. Show How the Same Junctions That Decouple the Wells Also Build a Parasitic Thyristor

The n-well/p-well junction, together with the source/drain diffusions sitting inside each well, does not only form the two MOS transistors it was intended to form. Read along the vertical cross-section, the n-well, the p-substrate (or p-well) beneath it, and the n+ and p+ diffusions at the surface form two parasitic bipolar transistors — one PNP, one NPN — wired base-to-collector with each other. This pair is a parasitic silicon-controlled rectifier, and once triggered it latches: it conducts a large current directly from $V_{dd}$ to ground through a low-impedance path that persists until power is removed, not until the triggering condition ends.

$$\beta_{PNP}\cdot\beta_{NPN}\ge 1 \implies \text{regenerative latchup}$$

The condition for latchup is a loop gain condition: if the product of the two parasitic transistors' current gains reaches or exceeds unity, the pair's feedback becomes self-sustaining. This parasitic structure existed in single-well CMOS too, but at 1963's device spacing the well-to-well distance was large enough, and the parasitic resistances in the loop high enough, that the loop gain stayed safely below the threshold. Shrinking that same spacing to 1980s density — the same density increase that made $P_{static}$ decisive in Step 1 — shrinks the physical separation between the NMOS and PMOS wells, which lowers the parasitic resistances that were previously suppressing the loop gain. The parasitic device was never removed between 1963 and 1980. Density simply pushed its loop gain toward the threshold it had always had.

Density Shrinks the Loop That Suppresses the Parasitic Thyristor Real Diagram — the PNP/NPN parasitic pair hiding inside every twin-well CMOS cross-section THE PARASITIC PAIR n-well/substrate/p+ forms PNP substrate/n-well/n+ forms NPN cross-coupled base-collector a parasitic SCR present since single-well CMOS loop gain β_PNP·β_NPN was always nonzero WHAT DENSITY CHANGES shrinking well-to-well spacing lowers parasitic shunt resistance resistance was suppressing loop gain 1963's spacing kept β_PNP·β_NPN < 1 safely 1980's spacing pushes toward β_PNP·β_NPN ≥ 1 LATCHUP: A LOW-IMPEDANCE PATH FROM V_dd TO GROUND conducts destructively until power is removed, not until the trigger condition ends process layout must restore the margin density removed — Section 3 guard rings and heavily doped substrate ties lower the shunt resistance back down deliberately — Step 3

## 3. Place Latchup in the Project's Own Pattern of Density Reopening Solved Problems

This is not the first time this project has shown density reopening a problem an earlier series considered settled. The 1974 trench/stacked-capacitor DRAM series opened on exactly this structure: a planar capacitor that worked perfectly well at low density until shrinking area forced a geometric rework. Latchup follows the identical shape at the circuit level rather than the device level — CMOS's complementary topology was correct and complete in 1963, the parasitic bipolar pair it quietly contains was always there, and only this series' density increase made that parasitic's loop gain threatening enough to require active countermeasures.

It is also worth being precise about what twin-well construction does and does not fix. Twin wells solve the independent-tuning problem from Section 1 — they let each device's body doping be optimized without being tied to the other's. They do not, by themselves, fix latchup; if anything, the tighter spacing that twin-well processes enable is exactly what makes the parasitic loop gain more dangerous, not less. Latchup is addressed separately, at the layout and process level, through guard rings and heavily doped substrate contacts that deliberately lower the parasitic shunt resistance Section 2 showed density had reduced. Step 3 takes up those specific layout countermeasures and the area penalty each one costs — the concrete price twin-well CMOS pays for density, continuing the project's running habit of quantifying exactly what a structural fix costs rather than treating "solved" as free.

Take cmos crossover 1980 twin well latchup density penalty further

Ask the copilot about this term, or have our engineers assess it against your process.

Ask CFSGPT about this → Request a technical assessment → Open the CFS app