CMOS Crossover 1980 Static Power Crosses the Line Nmos Could Not Defend

# Why a Current That Never Turns Off Becomes the Deciding Term NMOS Cannot Scale Away

## 1. Separate the Power Term HMOS Could Manage From the One It Could Not

HMOS pushed the NMOS depletion-load inverter about as far as a single device family could go: Steps 2 through 8 of the 1978 series redesigned the load, thinned the oxide, and rebuilt the interconnect, and Step 9 showed the resulting power-delay product still trailing CMOS on paper. What that series' own accounting could not make disappear was not dynamic power — the $CV_{dd}^2f$ term Step 1 of 1978 already identified and that every subsequent HMOS refinement chipped away at. It was a second, structurally different term that ratioed NMOS logic can never remove by any amount of process tuning: static power.

In a depletion-load NMOS inverter, current flows through the load-and-switch path whenever the output sits low — which, averaged over a running program, is a substantial fraction of the time. This is not leakage in the parasitic sense; it is current the circuit's own topology requires to hold a logic state:

$$P_{static}=I_{DD}\,V_{dd},\qquad I_{DD}>0 \text{ whenever output} = \text{LOW}$$
$$P_{total}=P_{static}+P_{dynamic}=I_{DD}V_{dd}+CV_{dd}^{2}f$$

Every prior series in this project's NMOS lineage — 1967's silicon gate, 1971's microprocessor, 1978's HMOS — scaled $P_{dynamic}$ down generation after generation. None of them touched $P_{static}$, because touching it meant abandoning the ratioed-inverter topology itself, not refining it.

Two Power Terms, Only One of Which Scaling Ever Touched P_total = P_static + P_dynamic — every HMOS refinement cut the second term only P_static = I_DD · V_dd current flows through load+switch whenever output sits LOW structural — topology requires it 1967 → 1971 → 1978 never reduced this term only removable by changing topology itself P_dynamic = C·V_dd²·f current flows only while switching between logic states process-tunable — every scaling lever works here 1978's oxide, load, interconnect fixes all targeted this this is the term HMOS actually reduced NO AMOUNT OF PROCESS REFINEMENT TOUCHES THE RED TERM it is a consequence of the ratioed-inverter circuit, not of any dimension HMOS shrank removing P_static requires changing which devices conduct 1962's complementary pair already showed how — Section 2

## 2. Show Why the Line Being Crossed Is Not a Process Line but an Architectural One

The 1962–1963 series already built the device pair that eliminates $P_{static}$ by construction: a complementary PMOS–NMOS pair in which, for any stable logic state, exactly one of the two transistors is off, and an off transistor ideally passes no current at all. $I_{DD}\approx 0$ in steady state is not a refinement CMOS earned through process tuning — it was true the moment the topology existed, in 1963, at whatever lithography node 1963 could manage. What changed between 1963 and 1980 was never the equation. It was which side of a cost comparison CMOS sat on.

$$P_{total,NMOS}=I_{DD}V_{dd}+C_NV_{dd}^2f,\qquad P_{total,CMOS}\approx C_CV_{dd}^2f$$

Through the 1960s and 1970s, $I_{DD}V_{dd}$ in a well-designed ratioed inverter was small enough, and CMOS's density and well-isolation penalty large enough, that NMOS's simplicity won on cost per function — this is exactly the comparison 1978's Step 9 quantified. The crossover this series documents is not a change in either equation. It is clock frequency $f$ and integration density both climbing far enough, across the 1970s NMOS lineage this project has now traced from 1967 through HMOS, that the number of transistors simultaneously holding a LOW output on a single die — each one contributing its own $I_{DD}V_{dd}$ — eventually produces aggregate static power that no longer looks small next to $C_NV_{dd}^2f$. The static term was always there. Only now is it large enough to decide the outcome.

The Crossover Is Density Rising, Not the Physics Changing Real Diagram — the same two equations, 1963 versus 1980 1963 few thousand transistors/die small aggregate I_DD·V_dd CMOS loses on density/cost 1980 hundreds of thousands/die large aggregate I_DD·V_dd CMOS wins on total power density × clock speed climb SAME I_DD·V_dd EQUATION IN BOTH YEARS 1962-63 built the zero-static-current topology; it did not need 17 more years to work it needed NMOS density to climb until the term it eliminates stopped being negligible THE LINE BEING CROSSED IS ECONOMIC, NOT PHYSICAL CMOS's well-isolation and area penalty must now be paid because the alternative — NMOS's static term at this density — costs more

## 3. Place the Crossover in the Project's Own Fork-and-Rejoin History

This series resumes a thread the project deliberately left open at two earlier points. The 1962–1963 series built CMOS first and explicitly noted it as a *fork* from the NMOS lineage, not a replacement for it — 1963's own closing section observed that CMOS's density and cost disadvantage meant the industry's dominant path would stay on NMOS for the foreseeable future. The 1978 HMOS series then pushed that NMOS path as far as a single device family could go, and its own Step 9 quantified the comparison this series now resolves: at 1978's density, NMOS still won; at the density this series opens with, it no longer does.

What this series is not is a discovery of new physics. The complementary pair, the well-isolation requirement, the latchup risk 1978's Step 9 already named as CMOS's density penalty — all of it was established in 1962 and 1963. What changed is which term in a cost equation dominates, and that change was driven entirely by how far the NMOS lineage — 1967, 1971, 1978 — had to push density and clock speed before static power stopped being a rounding error. The next step takes up what actually has to happen at the process level to make a seventeen-year-old topology manufacturable at 1980s density and cost: twin-well CMOS, and the latchup problem that denser complementary pairs reintroduce at exactly the scale this crossover now demands.

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